Semiconductor reliability test chip
First Claim
Patent Images
1. A test chip for testing a plurality of functions thereof comprising:
- a MOS substrate including a periphery having at least four sides, a plurality of contact pads located substantially adjacent at least a portion of at least one side of the periphery of the MOS substrate, at least a portion of the plurality of contact pads being located in a first row and a second row located substantially adjacent the first row on the at least a portion of the at least one side of the periphery of the MOS substrate, the plurality of contact pads including more than one geometric shape, more than one geometric size and at least a portion of one conductive line located substantially in a scribe area extending about at least a portion of the periphery of the MOS substrate.
0 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.
-
Citations
16 Claims
-
1. A test chip for testing a plurality of functions thereof comprising:
-
a MOS substrate including a periphery having at least four sides, a plurality of contact pads located substantially adjacent at least a portion of at least one side of the periphery of the MOS substrate, at least a portion of the plurality of contact pads being located in a first row and a second row located substantially adjacent the first row on the at least a portion of the at least one side of the periphery of the MOS substrate, the plurality of contact pads including more than one geometric shape, more than one geometric size and at least a portion of one conductive line located substantially in a scribe area extending about at least a portion of the periphery of the MOS substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
a plurality of conductive lines located substantially in the scribe area of the MOS substrate extending substantially throughout the periphery of the MOS substrate, at least two lines of the plurality of conductive lines having a width which differs from one another, each line of the plurality of conductive lines having a spacing which differs from another line of the plurality of conductive lines.
-
-
4. The test chip of claim 1, wherein the plurality of contact pads is formed in a plurality of groups of contact pads, each group of contact pads extending substantially about one side of the periphery of the MOS substrate, each individual group of contact pads being of a different size than another group of contact pads of the plurality of groups of contact pads, the plurality of groups of contact pads extending substantially about the at least a portion of the at least one side of the periphery of the MOS substrate, each group of the plurality of groups of contact pads including at least a first row of contact pads and at least a second row of contact pads located adjacent the at least a first row of contact pads, some of the contact pads having a polysilicon area located thereunder, the polysilicon area having at least two differing configurations.
-
5. The test chip of claim 1, wherein the MOS substrate further includes:
a plurality of resistive-type heaters located on a portion of the MOS substrate, each resistive-type heater of the plurality of resistive-type heaters independently connected to a connector pad on the MOS substrate.
-
6. The test chip of claim 1, wherein the MOS substrate further includes:
a plurality of transistors to measure any temperature gradient in the MOS substrate.
-
7. The test chip of claim 1, wherein the MOS substrate further includes:
a plurality of thin gate and thick gate transistor devices for measurement of temperature or ion contamination of the MOS substrate.
-
8. The test chip of claim 1, wherein the MOS substrate further includes:
a plurality of resistors for measurement of thermal performance of a portion of the MOS substrate and any package in which it is mounted.
-
9. The test chip of claim 1, wherein the MOS substrate further includes:
a plurality of flip chip test pads located substantially in a center portion of the MOS substrate.
-
10. The test chip of claim 1, wherein the MOS substrate further includes:
a plurality of flip chip test pads in an array located substantially in a center portion of the MOS substrate, a portion of the plurality of flip chip test pads being connected in a daisy chain connection by conductors extending therebetween, the portion of the plurality of flip chip test pads being connected in the daisy chain connection being independent of other flip chip test pads of the plurality of flip chip test pads.
-
11. A semiconductor chip for testing comprising:
-
a MOS substrate including a periphery formed by a plurality of sides, a plurality of contact pads located substantially adjacent a portion of the periphery of the MOS substrate, the plurality of contact pads having a plurality of geometric shapes, the plurality of contact pads forming a plurality of groups of contact pads extending substantially about at least a portion of at least two sides of the periphery of the MOS substrate, each group of the plurality of groups of contact pads including at least a first row of contact pads and at least a second row of contact pads located adjacent the at least a first row of contact pads, a portion of the plurality of contact pads including active circuitry of the MOS substrate. - View Dependent Claims (12, 13, 14, 15, 16)
a plurality of conductive lines located substantially in a scribe area of the MOS substrate extending substantially throughout the periphery of the MOS substrate, at least two lines of the plurality of conductive lines having a width which differs from one another, each line of the plurality of conductive lines having a spacing which differs from another line of the plurality of conductive lines.
-
-
14. The semiconductor chip of claim 11, wherein each group of the plurality of groups of contact pads extends substantially about one side of the periphery of the MOS substrate, each individual group of contact pads being of a different size than another group of contact pads of the plurality of contact pads, the plurality of groups of contact pads extending substantially about the portion of the periphery of the MOS substrate, each group of the plurality of groups of contact pads including at least a first row of contact pads and at least a second row of contact pads located adjacent the at least a first row of contact pads, some of the contact pads having a polysilicon area located thereunder, the polysilicon area having at least two differing configurations.
-
15. The semiconductor chip of claim 11, wherein the semiconductor chip further includes:
a plurality of resistive-type heaters located on a portion of the MOS substrate, each resistive-type heater of the plurality of resistive-type heaters independently connected to a connector pad on the MOS substrate.
-
16. The semiconductor chip of claim 11, wherein the semiconductor chip further includes at least one of:
-
a plurality of transistors to measure any temperature gradient in the MOS substrate;
a plurality of thin gate and thick gate transistor devices for measurement of temperature or ion contamination of the MOS substrate;
a plurality of resistors for measurement of thermal performance of a portion of the MOS substrate and any package in which it is mounted; and
a plurality of flip chip test pads located substantially in a center portion of the MOS substrate.
-
Specification