System and method for testing integrated circuit modules

• US 6,771,087 B1
• Filed: 06/04/2002
• Issued: 08/03/2004
• Est. Priority Date: 06/04/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Oz, Oved, Mizrahi, Abraham
• Primary Examiner(s): TANG, MINH NHUT
• Application Number:
  US10/162,421
• Time in Patent Office: 791 Days
• Field of Search: 324/73.1, 324/763-765, 324/158.1, 714/724-725, 714/733-734, 702/118-120
• US Class Current: 324/762.02
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G01R 31/318572 Input/Output interfaces

Abstract

Verification testing of modules packaged within an integrated circuit are conducted utilizing I/O ports of the integrated circuit for inputting or outputting incoming and outgoing signals, with three sets of externally controlled, tri-state buffers provided for each module. A first set selectively connects predetermined I/O contacts of each module interconnected to contacts of other modules, a second set selectively connects predetermined I/O contacts of each module to the I/O ports and a common test bus, and a third set applies the last logic state on each I/O contact before isolation by a buffer from the first set. Whenever a module is selected for testing, the current value that appears on each I/O contact that is connected to other modules is stored in its corresponding bus holder, so as to essentially prevent DC leakage currents.

Claims

1. A system for verification testing of modules within an integrated circuit comprising:

one or more modules each having input/output contacts coupled to input/output contacts of each other module by a common test bus;

a set of first externally controlled buffers selectively coupling the common test bus to input/output ports for the integrated circuit; and

one or more sets of second externally controlled buffers each selectively coupling input/output contacts of a corresponding module to the common test bus;

wherein

each of the first and second externally controlled buffers is a tri-state buffer.

2. The system according to claim 1, further comprising:

externally controlled bus holders each connecting an output of an externally controlled buffer of the one or more sets of second externally controlled buffers selectively coupling input contacts of a corresponding module to the common test bus with an input contact of another module, wherein the bus holders preserve a logic state appearing on the input contacts of the corresponding module prior to isolation of the input contacts of the corresponding module by the respective externally controlled buffer of the one or more sets of second externally controlled buffers.

3. The system according to claim 2, wherein the externally controlled bus holders each comprise a pair of serially connected inverters including at least one externally controlled tri-state inverter.

4. The system according to claim 1, wherein, during verification testing of the modules within the integrated circuit, input/output contacts for each module other than a selected module are isolated from the common test bus by associated externally controlled buffers of the one or more sets of second externally controlled buffers.

5. The system according to claim 1, wherein, during operation of the integrated circuit in a functional mode, input/output ports for the integrated circuit are isolated from the common test bus by associated externally controlled buffers of the set of first externally controlled buffers.

6. The system according to claim 5, further comprising:

one or more functional buses separate from the common test bus and coupling the input/output ports of the integrated circuit to the one or more modules.

7. A system for verification testing of modules within an integrated circuit comprising:

a common test bus coupling input/output contacts of all modules;

externally controlled test-mode buffers selectively connecting the common test bus to input/output ports for the integrated circuit; and

a plurality of sets of externally controlled module-select buffers each associated with a different module and selectively coupling input/output contacts of the associated module to the common test bus;

wherein

each of the externally controlled test-mode and module-select buffers is a tri-state buffer.

8. The system according to claim 7, further comprising:

externally controlled bus holders each connecting at least one output of an externally controlled module-select buffer with an input contact of another module, wherein the at least one output selectively connects an input contact for an associated module to the common test bus, and wherein the bus holders preserve a logic state appearing on the input contacts of the corresponding module prior to isolation of the input contacts of the corresponding module by a respective externally controlled module-select buffer.

9. The system according to claim 8, wherein the externally controlled bus holders each comprise a pair of serially connected inverters including at least one externally controlled tri-state inverter.

10. The system according to claim 7, wherein, during verification testing of the modules within the integrated circuit, input/output contacts for each module other than a selected module are isolated from the common test bus by associated externally controlled module-select buffers.

11. The system according to claim 7, wherein, during operation of the integrated circuit in a functional mode, input/output ports for the integrated circuit are isolated from the common test bus by associated externally controlled test-mode buffers.

12. The system according to claim 11, further comprising:

one or more functional buses separate from the common test bus and coupling the input/output ports of the integrated circuit to the one or more modules.

13. A method for verification testing of modules within an integrated circuit comprising:

coupling input/output contact for one or more modules by a common test bus;

selectively coupling the common test bus to input/output ports for the integrated circuit through a first set of tri-stateable buffers; and

selectively coupling input/output contacts of each corresponding module to the common test bus through a second set of tri-stateable buffers.

14. The method according to claim 13, further comprising:

preserving a logic state appearing on input contacts of a selected module prior to isolation of the input contacts of the selected module; and

transmitting the preserved logic state to input contacts of another module.

15. The method according to claim 14, further comprising:

employing externally controlled bus holders each comprising a pair of serially connected inverters including at least one externally controlled tri-state inverter.

16. The method according to claim 13, further comprising:

during verification testing of the modules within the integrated circuit, isolating input/output contacts for each module other than a selected module from the common test bus by associated externally controlled buffers of the second set of tri-stateable buffers.

17. The method according to claim 13, further comprising:

during operation of the integrated circuit in a functional mode, isolating input/output ports for the integrated circuit from the common test bus by associated externally controlled buffers of the first set of tri-stateable buffers and employing one or more functional buses separate from the common test bus to couple the input/output ports of the integrated circuit to the one or more modules.

18. An integrated circuit system comprising:

a first module comprising a first input, a first output and a second output;

a second module comprising a first input, and a first output;

a first buffer comprising a first output coupled to the first input of the first module, and a first input coupled to a test bus;

a second buffer comprising a first output, coupled to the first input of the first buffer, and a first input, coupled to a first input port of the integrated circuit and to a first functional bus;

a third buffer comprising a first input coupled to the first output of the first module, and a first output coupled to the test bus;

a fourth buffer comprising a first input, coupled to the first output of the third buffer, and a first output, coupled to a first output port of the integrated circuit and to a second functional bus.

19. The system of claim 18, wherein the first buffer, second buffer, third buffer and fourth buffer are tri-state buffers.

20. The system of claim 18, further comprising:

fifth buffer comprising a first input coupled to the second output of the first module, and a first output coupled to the first input of the second module.

21. The system of claim 18, further comprising:

a logic state holder coupled to the first input of the first module.

22. The system of claim 18, further comprising:

a fifth buffer comprising a first output coupled to the first input of the second module, and a first input coupled to the first input of the first buffer; and

a sixth buffer comprising a first input coupled to the first output of the second module, and a first output coupled to the first output of the third buffer.