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System and method for testing integrated circuit modules

  • US 6,771,087 B1
  • Filed: 06/04/2002
  • Issued: 08/03/2004
  • Est. Priority Date: 06/04/2001
  • Status: Active Grant
First Claim
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1. A system for verification testing of modules within an integrated circuit comprising:

  • one or more modules each having input/output contacts coupled to input/output contacts of each other module by a common test bus;

    a set of first externally controlled buffers selectively coupling the common test bus to input/output ports for the integrated circuit; and

    one or more sets of second externally controlled buffers each selectively coupling input/output contacts of a corresponding module to the common test bus;

    wherein each of the first and second externally controlled buffers is a tri-state buffer.

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