CMOS Amplifier for optoelectronic receivers

• US 6,771,131 B2
• Filed: 05/09/2002
• Issued: 08/03/2004
• Est. Priority Date: 05/09/2002
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wilson, Timothy M., Karnick, Tanay, Jaussi, James E., Casper, Bryan K., Martin, Aaron K.
• Primary Examiner(s): Nguyen, Khanh V.
• Application Number:
  US10/142,492
• Publication Number:
  US 20030210097A1
• Time in Patent Office: 817 Days
• Field of Search: 330/258, 330/308
• US Class Current: 330/308
• CPC Class Codes: H03F 2203/45644 the LC comprising a cross coupling circuit, e.g. comprising two cross-coupled transistors
• CPC Class Codes: H03F 2203/45728 the LC comprising one switch
• CPC Class Codes: H03F 3/082 with FET's H03F3/085 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence

Abstract

A CMOS amplifier for optoelectronic receivers, the amplifier comprises two transimpedance amplifiers and two differential amplifier latches. One of the two transimpedance amplifiers has an input port to receive a current signal, such as, for example, a current signal from a photodetector, and provides a output voltage indicative of the received current signal. The other of the two transimpedance amplifiers may be viewed as having no input signal, so that it provides a reference voltage. The two transimpedance amplifiers are in close proximity to each other, so that power supply noise is a common mode signal in the output voltages of the two transimpedance amplifiers. The differential amplifier latches reject the common mode signal by comparing the reference voltage to the output voltage, and provide output logic voltages indicative of binary hard decisions. Two differential amplifier latches are employed, each with an evaluation phase on alternate transitions of a clock signal, so as to provide a higher throughput than if only one differential amplifier latch was employed.

Claims

1. An amplifier comprising an input port to receive a current signal, the amplifier comprising:

a first transimpedance amplifier to provide an output voltage indicative of the received current signal;

a second transimpedance amplifier to provide a reference voltage; and

a first differential amplifier latch to provide during an evaluation phase an output logic voltage indicative of whether the output voltage of the first transimpedance amplifier is greater or lesser than the reference voltage;

wherein the first and second transimpedance amplifiers are in close proximity to each other so that power supply noise is a common mode signal in the reference voltage and in the output voltage of the first transimpedance amplifier.

2. The amplifier as set forth in claim 1, wherein the first and second transimpedance amplifiers are identical in circuit layout.

3. The amplifier as set forth in claim 1, further comprising:

a second differential amplifier latch to provide during an evaluation phase an output logic voltage indicative of whether the output voltage of the first transimpedance amplifier is greater or lesser than the reference voltage;

wherein the first and second differential amplifiers are coupled so as to enter their respective evaluation phases on alternate transitions of a clock signal.

4. A die comprising:

a ground rail;

a power rail;

an amplifier comprising

an input port to receive a current signal;

a first output port to provide an output voltage indicative of the current signal;

a second output port to provide a reference voltage;

a first transimpedance amplifier comprising

a first common-gate transistor comprising a drain coupled to the first output port, and a source connected to the input port;

a first pMOSFET bias transistor comprising a drain connected to the source of the first common-gate transistor, and a gate connected to the ground rail; and

a first uMOSFET bias transistor comprising a drain connected to the drain of the first common-gate transistor, and a gate connected to the power rail;

a second transimpedance amplifier comprising

a second common-gate transistor comprising a drain coupled to the second output port, and a source,

a second pMOSFET bias transistor comprising a drain connected to the source of the second common-gate transistor, and a gate connected to the ground rail; and

a second nMOSFET bias transistor comprising a drain connected to the drain of the second common-gate transistor, and a gate connected to the power rail; and

a first differential amplifier latch to provide an output logic voltage during an evaluation phase indicative of comparing the reference voltage with the output voltage.

5. The die as set forth in claim 4, wherein

the first transimpedance amplifier further comprises at least one voltage amplifier stage comprising an input port connected to the drain of the first common-gate transistor and an output port to provide the output voltage; and

the second transimpedance amplifier further comprises at least one voltage amplifier stage comprising an input port connected to the drain of the second common-gate transistor and an output port to provide the reference voltage.

6. The die as set forth in claim 5, the amplifier further comprising:

a second differential amplifier latch to provide an output logic voltage during an evaluation phase indicative of whether the output voltage of the first transimpedance amplifier is greater or lesser than the reference voltage;

wherein the first and second differential amplifiers are coupled so as to enter their respective evaluation phases on alternate transitions of a clock signal.

7. The die as set forth in claim 4, the amplifier further comprising:

a second differential amplifier latch to provide an output logic voltage during an evaluation phase indicative of whether the output voltage of the first transimpedance amplifier is greater or lesser than the reference voltage;

wherein the first and second differential amplifiers are coupled so as to enter their respective evaluation phases on alternate transitions of a clock signal.

8. A computer system comprising:

a photodetector comprising an output port; and

an amplifier comprising an input port to receive a current signal, the amplifier comprising;

a first transimpedance amplifier to provide an output voltage indicative of the received current signal;

a second transimpedance amplifier to provide a reference voltage; and

a first differential amplifier latch to provide during an evaluation phase an output logic voltage indicative of whether the output voltage of the first transimpedance amplifier is greater or lesser than the reference voltage;

wherein the first and second transimpedance amplifiers are in close proximity to each other so that power supply noise is a common mode signal in the reference voltage and in the output voltage of the first transimpedance amplifier.

9. The computer system as set forth in claim 8, wherein the first and second transimpedance amplifiers are identical in circuit layout.

10. The computer system as set forth in claim 8, the amplifier further comprising:

a second differential amplifier latch to provide during an evaluation phase an output logic voltage indicative of whether the output voltage of the first transimpedance amplifier is greater or lesser than the reference voltage;

wherein the first and second differential amplifiers are coupled so as to enter their respective evaluation phases on alternate transitions of a clock signal.

11. An amplifier comprising:

a first transimpedance amplifier comprising an input port and an output port to provide a output voltage at its output port indicative of a signal current at its input port;

a second transimpedance amplifier identical in circuit layout to the first transimpedance amplifier, wherein the second transimpedance amplifier comprises an input port and an output port corresponding to the input port and the output port of the first transimpedance amplifier, respectively, wherein the input port of the second transimpedance amplifier receives no signal current and the output port of the second transimpedance amplifier provides a reference voltage; and

a first differential amplifier latch to provide during an evaluation phase an output logic voltage indicative of whether the output voltage of the first transimpedance amplifier is greater or lesser than the reference voltage.

12. The amplifier as set forth in claim 11, wherein the first and second transimpedance amplifiers have a symmetrical layout so that power supply noise is a common mode signal in the reference voltage and in the output voltage of the first transimpedance amplifier.

13. The amplifier as set forth in claim 12, further comprising:

a second differential amplifier latch to provide during an evaluation phase an output logic voltage indicative of whether the output voltage of the first transimpedance amplifier is greater or lesser than the reference voltage;

wherein the first and second differential amplifiers are coupled so as to enter their respective evaluation phases on alternate transitions of a clock signal.

14. An amplifier comprising:

a first transimpedance amplifier comprising an input port and an output port to provide a output voltage at its output port indicative of a signal current at its input port;

a second transimpedance amplifier identical in circuit layout to the first transimpedance amplifier, wherein the second transimpedance amplifier comprises an input port and an output port corresponding to the input port and the output port of the first transimpedance amplifier, respectively, wherein the input port of the second transimpedance amplifier receives no signal current and the output port of the second transimpedance amplifier provides a reference voltage; and

wherein the first and second transimpedance amplifiers have a symmetrical layout so that power supply noise is a common mode signal in the reference voltage and in the output voltage of the first transimpedance amplifier.