Semiconductor memory device and control method

• US 6,771,552 B2
• Filed: 02/21/2003
• Issued: 08/03/2004
• Est. Priority Date: 02/21/2002
• Status: Expired due to Fees

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Fujisawa, Hiroki
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US10/372,604
• Publication Number:
  US 20030156481A1
• Time in Patent Office: 529 Days
• Field of Search: 365/221, 365/220, 365/189.01, 365/189.04, 365/193, 365/233, 365/230.06, 365/239
• US Class Current: 365/221
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

In a semiconductor memory device in which a system clock that is supplied from the outside and a data strobe signal that is received as input and supplied as output in synchronization with data are used to control operations for reading and writing data, the transmission of write data from FIFO memories to write amplifiers is controlled by the data strobe signal. In addition, switches for connecting write amplifiers with bit lines that are linked to memory cells that correspond to addresses to which write data are to be written are driven without delaying with respect to a timing signal that is synchronized with the system clock. Write data that have been received as burst input are transmitted in parallel from the FIFO memories to the write amplifiers in units of the prefetch number.

Claims

1. A semiconductor memory device in which operations for writing and reading data are controlled by using a system clock that is supplied from the outside and a data strobe signal that is received as input and supplied as output in synchronization with said data;

said semiconductor memory device comprising;

a plurality of FIFO memories for temporarily holding write data, which are received as input from the outside and which are the object of writing;

a plurality of write amplifiers for writing said write data to memory cells that correspond to addresses that are received as input from the outside;

a first write-system control circuit for generating a first control signal for causing said write data to be transmitted from said FIFO memories to said write amplifiers in synchronization with said data strobe signal that is received together with, of said write data that have been received as burst input for one write command, the final item of write data of every prefetch number of items of write data;

a Y-system control circuit for generating a second control signal for driving a plurality of switches, which connect said write amplifiers with bit lines that connect to memory cells that correspond to addresses to which said write data are written, in synchronization with, of said system clock, the pulse edge of a prescribed cycle following completion of input of said final item of write data; and

a second write-system control circuit for generating a third control signal for causing a write voltage, which is a voltage that is required for writing data to said memory cells, to be supplied as output from said write amplifiers based on said write data in synchronization with, of said system clock, the pulse edge after a prescribed cycle following the completion of input of said final item of write data.

2. The semiconductor memory device according to claim 1, wherein said FIFO memories comprise:

a serial-parallel conversion circuit for supplying said write data, which have been received as said burst input, as parallel output in units of said prefetch number.

3. The semiconductor memory device according to claim 1, wherein said Y-system control circuit:

upon receiving a read command for reading data that have been stored in said memory cells, delays said second control signal a prescribed time interval from a timing signal that is synchronized with said system clock and supplies said second control signal as output; and

upon receiving a write command for writing said write data to said memory cells, supplies said second control signal as output without delaying said second control signal from a timing signal that is synchronized with said system clock.

4. A control method of a semiconductor memory device, said semiconductor memory device being provided with:

a plurality of FIFO memories for temporarily holding write data, which are data that are received as input from the outside and which are the object of writing; and

a plurality of write amplifiers for writing said write data to memory cells that correspond to addresses that are received as input from the outside; and

said semiconductor memory device using a system clock that is supplied from the outside and a data strobe signal that is received as input and supplied as output in synchronization with data to control the operations of writing and reading said data;

said control method comprising the steps of;

transferring said write data from said FIFO memories to said write amplifiers in synchronization with said data strobe signal that is received as input together with, of write data that are received as burst input for one write command, the final item of write data of a prefetch number of items of write data;

driving a plurality of switches for connecting said write amplifiers with bit lines, which are connected to memory cells that correspond to addresses to which said write data are to be written, in synchronization with, of said system clock, a pulse edge after a prescribed cycle following completion of input of said final item of write data; and

supplying write voltage, which is the voltage required for writing data to said memory cells, from said write amplifiers based on said write data.

5. The control method of a semiconductor memory device according to claim 4, wherein said write data that have been received as burst input are transmitted from said FIFO memories to said write amplifiers in parallel in units of said prefetch number.

6. The control method of a semiconductor memory device according to claim 4;

wherein;

when a read command for reading data that are stored in said memory cells is issued, said switches are driven after delaying a prescribed time interval from a timing signal that is synchronized with said system clock; and

when a write command is issued for writing said write data to said memory cells, said switches are driven without delaying from a timing signal that is synchronized with said system clock.