Multi-pixel methods and apparatus for analysis of defect information from test structures on semiconductor devices
First Claim
1. A method for detecting electrical defects on test structures of a semiconductor die, the test structures including a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures, the test structures each having a portion located partially within a scan area, the method comprising:
- a. scanning the portion of the test structures located within the scan area to obtain voltage contrast images of the test structures'"'"' portions; and
b. analyzing the obtained voltage contrast images to determine whether there are defects present within the test structures, wherein the obtained voltage contrast images have a pixel resolution size which is greater than a dimension of the test structures.
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Abstract
Disclosed is a method for detecting electrical defects on test structures of a semiconductor die. The test structures includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. The test structures each has a portion located partially within a scan area. The portion of the test structures located within the scan area is scanned to obtain voltage contrast images of the test structures'"'"' portions. In a multi-pixel processor, the obtained voltage contrast images are analyzed to determine whether there are defects present within the test structures. In a preferred embodiment, the multi-pixel processor operates with pixel resolution sizes in a range of about 25 nm to 200 nm. In another aspect, the processor operates with a pixel size nominally equivalent to two times a width of the test structure'"'"'s line width to maximize throughput at optimal signal to noise sensitivity. A computer readable medium having programming instructions for performing the above described methods is also disclosed.
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Citations
27 Claims
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1. A method for detecting electrical defects on test structures of a semiconductor die, the test structures including a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures, the test structures each having a portion located partially within a scan area, the method comprising:
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a. scanning the portion of the test structures located within the scan area to obtain voltage contrast images of the test structures'"'"' portions; and
b. analyzing the obtained voltage contrast images to determine whether there are defects present within the test structures, wherein the obtained voltage contrast images have a pixel resolution size which is greater than a dimension of the test structures. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer-readable medium comprising computer code for detecting electrical defects on test structures of a semiconductor die, the test structures including a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures, the test structures each having a portion located partially within a scan area, the computer-readable medium comprising:
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computer code for obtaining voltage contrast images of the portions of the test structures located within the scan area; and
computer code for analyzing the obtained voltage contrast images to determine whether there are defects present within the test structures, wherein the obtained voltage contrast images have a pixel resolution size which is greater than a dimension of the test structures. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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Specification