Multi-pixel methods and apparatus for analysis of defect information from test structures on semiconductor devices

• US 6,771,806 B1
• Filed: 08/25/2000
• Issued: 08/03/2004
• Est. Priority Date: 12/14/1999
• Status: Expired due to Term

• Current Assignee: KLA-Tencor Corporation (KLA Corporation)
• Original Assignee: KLA-Tencor Corporation (KLA Corporation)
• Inventors: Tsai, Bin-Ming Benjamin, Walker, David J., Satya, Akella V. S., Adler, David L.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): STEVENSON, ANDRE C
• Application Number:
  US09/648,381
• Time in Patent Office: 1,439 Days
• Field of Search: 438/14, 382/149, 382/141, 324/751
• US Class Current: 382/149
• CPC Class Codes: G01N 21/66 electrically excited, e.g. electroluminescence
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Disclosed is a method for detecting electrical defects on test structures of a semiconductor die. The test structures includes a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures. The test structures each has a portion located partially within a scan area. The portion of the test structures located within the scan area is scanned to obtain voltage contrast images of the test structures'"'"' portions. In a multi-pixel processor, the obtained voltage contrast images are analyzed to determine whether there are defects present within the test structures. In a preferred embodiment, the multi-pixel processor operates with pixel resolution sizes in a range of about 25 nm to 200 nm. In another aspect, the processor operates with a pixel size nominally equivalent to two times a width of the test structure'"'"'s line width to maximize throughput at optimal signal to noise sensitivity. A computer readable medium having programming instructions for performing the above described methods is also disclosed.

Claims

1. A method for detecting electrical defects on test structures of a semiconductor die, the test structures including a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures, the test structures each having a portion located partially within a scan area, the method comprising:

a. scanning the portion of the test structures located within the scan area to obtain voltage contrast images of the test structures'"'"' portions; and

b. analyzing the obtained voltage contrast images to determine whether there are defects present within the test structures, wherein the obtained voltage contrast images have a pixel resolution size which is greater than a dimension of the test structures.

2. A method as recited in claim 1 wherein the obtained voltage contrast images have pixel resolution sizes in a range of about 25 nm to 2000 nm.

3. A method as recited in claim 1, wherein the obtained voltage contrast images have a pixel size nominally equivalent to two times a width of the test structure'"'"'s line width to maximize throughput at optimal signal to noise sensitivity.

4. A method as recited in claim 1 wherein the scanned portions of the electrically isolated test structures are expected to have substantially a same first brightness level, and the scanned portions of the non-electrically isolated test structures are expected to have substantially a same second brightness level that differs from the first brightness level.

5. A method as recited in claim 1 wherein the obtained voltage contrast images are analyzed by comparing them to a plurality of reference images.

6. A method as recited in claim 3 wherein the reference images are generated from a database.

7. A method as recited in claim 6 wherein the database comprises expected voltage contrast images.

8. A method as recited in claim 6 wherein the database is a design database utilized to fabricate the semiconductor die.

9. A method as recited in claim 1 wherein the obtained voltage contrast images are analyzed by comparing them to a truth table.

10. A method as recited in claim 9 wherein the truth table includes expected brightness levels for the scanned portions of the test structures.

11. A method as recited in claim 1 wherein the obtained voltage contrast images are analyzed by comparing them to a plurality of images from an adjacent semiconductor die.

12. A method as recited in claim 1 wherein the obtained voltage contrast images are analyzed by comparing them to a plurality of images from an adjacent other plurality of test structures on the semiconductor die.

13. A method as recited in claim 10 wherein the comparison is accomplished in an array mode.

14. A method as recited in claim 1 wherein the scanning is accomplished with an electron beam.

15. A computer-readable medium comprising computer code for detecting electrical defects on test structures of a semiconductor die, the test structures including a plurality of electrically-isolated test structures and a plurality of non-electrically-isolated test structures, the test structures each having a portion located partially within a scan area, the computer-readable medium comprising:

computer code for obtaining voltage contrast images of the portions of the test structures located within the scan area; and

computer code for analyzing the obtained voltage contrast images to determine whether there are defects present within the test structures, wherein the obtained voltage contrast images have a pixel resolution size which is greater than a dimension of the test structures.

16. A computer-readable medium as recited in claim 15 wherein the images of the portions of the electrically isolated test structures are expected to have substantially a same first brightness level, and the image of the portions of the non-electrically isolated test structures are expected to have substantially a same second brightness level that differs from the first brightness level.

17. A computer-readable medium as recited in claim 15 wherein the obtained voltage contrast images are analyzed by comparing them to a plurality of reference images.

18. A computer-readable medium as recited in claim 17 wherein the reference images are generated from a database.

19. A computer-readable medium as recited in claim 18 wherein the database comprises expected voltage contrast images.

20. A computer-readable medium as recited in claim 18 wherein the database is a design database utilized to fabricate the semiconductor die.

21. A computer-readable medium as recited in claim 15 wherein the obtained voltage contrast images are analyzed by comparing them to a truth table.

22. A computer-readable medium as recited in claim 21 wherein the truth table includes expected brightness levels for the scanned portions of the test structures.

23. A computer-readable medium as recited in claim 15 wherein the obtained voltage contrast images are analyzed by comparing them to a plurality of images from an adjacent semiconductor die.

24. A computer-readable medium as recited in claim 15 wherein the obtained voltage contrast images are analyzed by comparing them to a plurality of images from an adjacent other plurality of test structures on the semiconductor die.

25. A computer-readable medium as recited in claim 24 wherein the comparison is accomplished in an array mode.

26. A computer-readable medium as recited in claim 15, wherein the obtained voltage contrast images have pixel resolution sizes in a range of about 25 nm to 200 nm.

27. A computer-readable medium as recited in claim 15, wherein the obtained voltage contrast images have a pixel size nominally equivalent to two times a width of the test structure'"'"'s line width to maximize throughput at optimal signal to noise sensitivity.