Flash memory system and method implementing LBA to PBA correlation within flash memory array

• US 6,772,274 B1
• Filed: 09/13/2000
• Issued: 08/03/2004
• Est. Priority Date: 09/13/2000
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Estakhri, Petro
• Primary Examiner(s): Gossage, Glenn
• Application Number:
  US09/660,838
• Time in Patent Office: 1,420 Days
• Field of Search: 711/103, 711/202, 711/209
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory

Abstract

A flash memory system is designed to reduce inefficiencies associated with keeping track of logical block address (LBA) to physical block address (PBA) correlation or mappmg—each logical block address generated by a host digital system and associated with data when the data is sent to be stored in the flash memory system by the host digital system. The flash memory system preferably comprises at least one flash memory device having a flash memory array, the flash memory array including a plurality, of blocks for storing data and for storing (LBA to PBA) correlation, each block having a plurality of sectors, and a controller coupled to each flash memory device, the controller including a new space manager. By removing from the space manager the task of tracking correlation between the LBA and the PBA, considerable savings in manufacturing costs and logic circuit area on an integrated circuit are achieved and design flexibility attained. The new space manager continues to keep track of the flags associated with the blocks in the flash memory system. However, sufficient blocks are specifically reserved for keeping track of the (LBA to PBA) correlation of the data stored in the flash memory system and are referred to as correlation blocks. In addition, the flash memory system avoids erase-before-write operations whenever possible during the process of keeping track of (LBA to PBA) correlation.

Claims

1. A flash memory device having at least one flash memory array for storing incoming data sent from a host system, the flash memory device comprising:

a plurality of separate, independently addressable, independently programmable and independently erasable non-volatile physical memory blocks distinguishably defined by a plurality of physical block addresses, including;

a. at least one data block for storing incoming data, a first data block defined by a first physical block address; and

b. at least one correlation block for storing correlation data within each flash memory array, a first correlation block defined by a second physical block address.

2. The flash memory device according to claim 1 wherein each physical memory block is identically comprised of a plurality of separately addressable sectors.

3. The flash memory device according to claim 2 wherein the sectors within the first data block each comprise a data field and an extension field, including a first sector defined by a first sector address, each data field capable of storing a logical block of incoming data defined by a logical block address selected from among a plurality of available logical block addresses, including a first logical block of incoming data defined according to a first logical block address stored in the first sector.

4. The flash memory device according to claim 3 wherein each sector within the first data block comprises an error correction code field and a flag field.

5. The flash memory device according to claim 3 wherein each correlation block is comprised of a plurality of separately addressable correlation sectors addressed according to a first set of sector addresses.

6. The flash memory device according to claim 5 wherein each sector within a correlation block is comprised of a plurality of fields for storing a physical block address.

7. The flash memory device according to claim 6 further comprising means for correlating a first predetermined range of logical block addresses to the first correlation block.

8. The flash memory device according to claim 7 wherein the means for correlating a first predetermined range of logical block addresses to the first correlation block comprises a volatile RAM array with a first register identifying the first correlation block.

9. The flash memory device according to claim 8 wherein the first register is further capable of identifying a current sector within the first correlation block.

10. The flash memory device according to claim 9 further comprising at least one alternate correlation block, wherein each alternate correlation block is configured to store a physical block address corresponding to a logical block address of data, further wherein each alternate correlation block is associated with a primary correlation block and wherein each alternate correlation block is configured to store physical block addresses corresponding to a predetermined range of logical block addresses associated with its primary correlation block.

11. The flash memory device according to claim 10 wherein if a free sector is not found in a primary correlation block, a physical block address corresponding to the logical block address of data and an unchanged correlation information from the current sector associated with the predetermined range of logical block addresses are stored in the alternate correlation block.

12. The flash memory device according to claim 11 wherein if a free sector is not found in an alternate correlation block, a physical block address corresponding to a logical block address of data and the unchanged correlation information from the current sector associated with the predetermined range of logical block addresses are stored in an erased primary correlation block.

13. A method of storing digital data within a flash memory system having at least one flash memory array comprising the steps of:

a. mapping a non-volatile memory medium within the flash memory system into a plurality of independently addressable, independently programmable and independently erasable nonvolatile physical memory blocks including a plurality of data blocks including a first data block defined by a first physical block address and at least one correlation block for storing correlation data within each flash memory array comprising a first correlation block defined by a second physical block address;

b. mapping each of the plurality of data blocks into a plurality of sectors, a plurality of sectors within the first data block distinguishably defined by sector addresses including a first sector defined by a first sector address;

c. mapping each correlation block into a plurality of sectors, the plurality of sectors within the first correlation block distinguishably defined by sector addresses including a second sector defined by a second sector address;

d. mapping each of the plurality of sectors within each correlation block into a plurality of fields, including a first field within the second sector, each field capable of storing a physical block address; and

e. assigning a first predetermined range of logical block addresses to the second physical block address and the second sector address, wherein the first predetermined range of logical block addresses contains a second predetermined range and a third predetermined range of logical block addresses.

14. The method according to claim 13 further comprising the steps:

a. determining that a correlation block is defective; and

b. allocating a non-defective block to replace the defective correlation block.

15. The method according to claim 13 further comprising a second flash memory system, the method further comprising the steps:

a. mapping a non-volatile memory medium within the second flash memory system into a plurality of independently addressable, independently programmable and independently erasable memory blocks including a plurality of data blocks including a second data block defined by a third physical block address and at least one correlation block comprising a second correlation block defined by a fourth physical block address;

b. mapping each of the plurality of data blocks within the second flash memory system into a plurality of sectors, a plurality of sectors within the second data block distinguishably defined by sector addresses including a third sector defined by a third sector address;

c. mapping each correlation block within the second flash memory system into a plurality of sectors, the plurality of sectors within the second correlation block distinguishably defined by sector addresses including a fourth sector defined by a fourth sector address;

d. mapping each of the plurality of sectors within each of the correlation blocks within the second flash memory system into a plurality of fields, including a first field within the fourth sector, each field capable of storing a physical block address; and

e. assigning a fourth predetermined range of logical block addresses to the fourth physical block address and the fourth sector address, wherein the fourth predetermined range of logical block addresses contains a fifth predetermined range and a sixth predetermined range of logical block addresses.

16. The method according to claim 15 further comprising the steps:

a. receiving from a host a first set of incoming data defined according to a first logical block address, the first logical block address being within the second predetermined range of logical block addresses;

b. storing the first set of incoming data in the second data block defined according to the third physical block address;

c. relating the second predetermined range of logical block addresses to the first field within the second sector; and

d. storing the third physical block address in the first field.

17. The method according to claim 16 wherein the first correlation block comprises a fifth sector defined by a fifth sector address incrementally following the second sector address, the fifth sector further comprising a second field and a third field, the method further comprising the steps:

a. receiving from a host a second set of incoming data defined according to a second logical block address, the second logical block address being within the third predetermined range of logical block addresses;

b. storing the second set of data in the a third data block defined according to a fifth physical block address, the third data block being located in the second flash memory system;

c. assigning the first predetermined range of logical block addresses to the second physical block address and the fifth sector address;

d. relating the second predetermined range of logical block addresses to the second field;

e. copying the third physical block address from the first field into the second field;

f. relating the third predetermined range of logical block addresses to the third field; and

g. storing the fifth physical block address in the third field.

18. The method according to claim 13 further comprising the steps:

a. receiving from a host a first set of incoming data defined according to a first logical block address, the first logical block address being within the second predetermined range of logical block addresses;

b. storing the first set of incoming data in the first data block defined according to the first physical block address;

c. relating the second predetermined range of logical block addresses to the first field within the second sector; and

d. storing the first physical block address in the first field.

19. The method according to claim 18 wherein the first correlation block comprises a third sector defined by a third sector address incrementally following the second sector address, the third sector further comprising a second field and a third field, the method further comprising the steps:

a. receiving from a host a second set of incoming data defined according to a second logical block address, the second logical block address being within the third predetermined range of logical block addresses;

b. storing the second set of incoming data in a second data block defined according to a third physical block address;

c. assigning the first predetermined range of logical block addresses to the second physical block address and the third sector address;

d. relating the second predetermined range of logical block addresses to the second field;

e. copying the first physical block address from the first field into the second field;

f. relating the third predetermined range of logical block addresses to the third field; and

g. storing the third physical block address in the third field.

20. The method according to claim 18 further comprising a second correlation block defined according to a third physical block address, the second correlation block comprising a third sector defined by a third sector address, the third sector further comprising a second field and a third field, the method further comprising the steps:

a. receiving from a host a second set of incoming data defined according to a second logical block address, the second logical block address being within the third predetermined range of logical block addresses;

b. storing the second set of incoming data in the second data block defined according to a fourth physical block address;

c. assigning the first predetermined range of logical block addresses to the third physical block address and the third sector address;

d. relating the second predetermined range of logical block addresses to the second field;

e. copying the first physical block address from the first field into the third field;

f. relating the third predetermined range of logical block addresses to the third field; and

g. storing the fourth physical block address in the third field.

21. The method according to claim 20 further comprising the step of erasing the first correlation block.