Method and apparatus for caching with variable size locking regions
First Claim
1. A method of managing data in a cache memory, comprising:
- mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines;
locking the first member of the plurality of cache lines creating a locked cache region and an unlocked cache region;
remapping the member of the plurality of memory addresses from the first member of the plurality of cache lines onto a second member of the plurality of cache lines within the unlocked cache region;
requesting data stored in the main memory;
fetching the data from the locked cache region, if available in the locked cache region;
fetching the data from the unlocked cache region, if not available in the locked cache region and available in the unlocked cache region; and
fetching the data from the main memory, if not available in the locked cache region and not available in the unlocked cache region.
3 Assignments
0 Petitions
Accused Products
Abstract
A method of managing data in a cache memory includes mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines, locking the first member of the plurality of cache lines creating a locked cache region and an unlocked cache region, remapping the member of the plurality of memory addresses from the first member of the plurality of cache lines onto a second member of the plurality of cache lines within the unlocked cache region, requesting data stored in the main memory, fetching the data from the locked cache region, if available in the locked cache region, fetching the data from the unlocked cache region, if not available in the locked cache region and available in the unlocked cache region, and fetching the data from the main memory, if not available in the locked cache region and not available in the unlocked cache region.
-
Citations
27 Claims
-
1. A method of managing data in a cache memory, comprising:
-
mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines;
locking the first member of the plurality of cache lines creating a locked cache region and an unlocked cache region;
remapping the member of the plurality of memory addresses from the first member of the plurality of cache lines onto a second member of the plurality of cache lines within the unlocked cache region;
requesting data stored in the main memory;
fetching the data from the locked cache region, if available in the locked cache region;
fetching the data from the unlocked cache region, if not available in the locked cache region and available in the unlocked cache region; and
fetching the data from the main memory, if not available in the locked cache region and not available in the unlocked cache region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
detecting whether the data is within the unlocked cache region, using a register that maintains a size of the unlocked cache region.
-
-
7. The method of claim 1, further comprising:
associating with the second member of the plurality of cache lines, a tag field to identify information stored in the second member of the plurality of cache lines.
-
8. The method of claim 7, the tag field comprising a sufficient width to support remapping of the member of the plurality of memory addresses onto a smallest possible portion of the unlocked cache region.
-
9. A method of managing data in a cache memory, comprising:
-
mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines;
locking the first member of the plurality of cache lines creating a locked cache region and an unlocked cache region;
remapping the member of the plurality of memory addresses from the first member of the plurality of cache lines onto a second member of the plurality of cache lines within the unlocked cache region;
requesting data stored in the main memory;
fetching the data from the locked cache region, if available in the locked cache region;
fetching the data from the unlocked cache region, if not available in the locked cache region and available in the unlocked cache region;
fetching the data from the main memory, if not available in the locked cache region and not available in the unlocked cache region;
detecting whether the data is within the unlocked cache region, using a register that maintains a size of the unlocked cache region; and
associating with the second member of the plurality of cache lines, a tag field to identify information stored in the second member of the plurality of cache lines.
-
-
10. A cache memory management system, comprising:
-
a main memory comprising a plurality of memory addresses; and
a cache memory comprising a plurality of cache lines, the plurality of cache lines comprising a locked cache region and an unlocked cache region;
wherein a member of the plurality of memory addresses is mapped onto a first member of the plurality of cache lines;
wherein the member of the plurality of memory addresses is configured to remap from the first member of the plurality of cache lines onto a second member of the plurality of cache lines;
wherein the first member of the plurality of cache lines is within the locked cache region, and the second member of the plurality of cache lines is within the unlocked cache region. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
a register maintaining a size of the unlocked cache region.
-
-
15. The cache memory management system of claim 10, further comprising:
an address detection mechanism configured to detect whether a referenced member of the plurality of memory addresses is within the locked cache region.
-
16. The cache memory management system of claim 10, further comprising:
a tag field associated with the second member of the plurality of cache lines to identify information stored therein.
-
17. The cache memory management system of claim 16, the tag field comprising a sufficient width to support remapping the member of the plurality of memory addresses onto the second member of the plurality of cache lines.
-
18. A cache memory management system, comprising:
-
a main memory comprising a plurality of memory addresses;
a cache memory comprising a plurality of cache lines, the cache memory comprising a locked cache region and an unlocked cache region;
a register maintaining a size of the unlocked cache region; and
an address detection mechanism configured to detect whether a referenced member of the plurality of memory addresses is within the locked cache region;
wherein a member of the plurality of memory addresses is mapped onto a first member of the plurality of cache lines;
wherein the member of the plurality of memory addresses is configured to remap from the first member of the plurality of cache lines onto a second member of the plurality of cache lines;
wherein the first member of the plurality of cache lines is within the locked cache region, and the second member of the plurality of cache lines is within the unlocked cache region.
-
-
19. A computer system for managing data in a cache memory, comprising:
-
a processor;
a memory;
software instructions stored in the memory to cause the computer system to perform;
mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines;
locking the first member of the plurality of cache lines creating a locked cache region and an unlocked cache region;
remapping the member of the plurality of memory addresses from the first member of the plurality of cache lines onto a second member of the plurality of cache lines within the unlocked cache region;
requesting data stored in the main memory;
fetching the data from the locked cache region, if available in the locked cache region;
fetching the data from the unlocked cache region, if not available in the locked cache region and available in the unlocked cache region; and
fetching the data from the main memory, if not available in the locked cache region and not available in the unlocked cache region. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
detecting whether the data is within the unlocked cache region, using a register that maintains a size of the unlocked cache region.
-
-
25. The computer system of claim 19, further comprising:
associating with the second member of the plurality of cache lines, a tag field to identify information stored in the second member of the plurality of cache lines.
-
26. The computer system of claim 25, the tag field comprising a sufficient width to support remapping of the member of the plurality of memory addresses onto a smallest possible portion of the unlocked cache region.
-
27. An apparatus managing data in a cache memory, comprising:
-
means for mapping a member of a plurality of memory addresses in a main memory onto a first member of a plurality of cache lines;
means for locking the first member of the plurality of cache lines creating a locked cache region and an unlocked cache region;
means for remapping the member of the plurality of memory addresses from the first member of the plurality of cache lines onto a second member of the plurality of cache lines within the unlocked cache region;
means for requesting data stored in the main memory;
means for fetching the data from the locked cache region, if available in the locked cache region;
means for fetching the data from the unlocked cache region, if not available in the locked cache region and available in the unlocked cache region; and
means for fetching the data from the main memory, if not available in the locked cache region and not available in the unlocked cache region.
-
Specification