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Processor architecture and operation for exploiting improved branch control instruction

  • US 6,772,325 B1
  • Filed: 10/01/1999
  • Issued: 08/03/2004
  • Est. Priority Date: 10/01/1999
  • Status: Expired due to Fees
First Claim
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1. A microprocessor comprising:

  • an instruction decoder decoding an instruction; and

    a plurality of address registers, each of which stores an address calculated based on address fields contained in one or more of said decoded instructions; and

    a plurality of instruction registers, each of which stores a target instruction related to a corresponding address held in one of said plurality of address registers;

    wherein a number of said plurality of address registers is greater than that of said plurality of instruction registers.

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