Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor

• US 6,772,403 B1
• Filed: 10/15/2002
• Issued: 08/03/2004
• Est. Priority Date: 04/21/2000
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sasaki, Yasuhiko
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): LIN, SUN J
• Application Number:
  US10/257,674
• Time in Patent Office: 658 Days
• Field of Search: 716/6, 716/4, 716/5
• US Class Current: 716/113
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

This is a method for more accurately calculating delay times in an electronic circuit device wherein signal arrival times on a victim wire and a plurality of aggressor wires adjacent thereto dynamically vary dependent on an input signal pattern by analyzing values of crosstalk-deriving delay degradation occurring between those wires. By utilizing delay degradation information searchable according to relative signal arrival times between the victim wire and the aggressor wires and adding delay degradations arising between the victim wire and the aggressor wires, calculated at every signal arrival time on the victim wire, the total delay degradation in the presence of a plurality of aggressor wires is calculated. Designing of a high-speed and large-scale electronic circuit device is facilitated and, because a superfluous margin regarding delay times can be eliminated, such electronic circuit devices can be efficiently designed and manufactured.

Claims

1. A crosstalk analysis method for analyzing signal crosstalk that a plurality of aggressor wires adjoining a victim wire inflict on said victim wire, the method comprising the steps of:

determining delay degradation that each of said plurality of aggressor wires inflicts on said victim wire according to a range that can be taken by the respective dynamic signal arrival times on said victim wire and said plurality of aggressor wires, and

adding said delay degradations with reference to the signal arrival time on said victim wire.

2. A crosstalk calculation method of an electronic circuit device for calculating crosstalk that a second and a third aggressor wires inflict on a first wire in the electronic circuit device having said second and said third aggressor wires which are arranged adjacent to said first wire, said first wire being connected to an output section of a first electronic circuit unit, said second and said third aggressor wires being connected to output sections of a second and a third electronic circuit unit respectively, the method comprising the steps of:

calculating a range of signal arrival time of each of said first wire and said second and said third aggressor wires on the basis of delay characteristics of signals in each of said first, said second and said third electronic circuit units,

determining delay degradation values due to crosstalk affecting said first wire according to timing of signals arriving on said second and said third wires on the basis of relative signal arrival times obtained by relative measuring of signal arrival times on said second and third wires with reference to a signal arrival time on said first wire, and

adding and said delay degradation values with reference to the signal arrival time on said first wire.

3. A crosstalk analysis method for analyzing signal crosstalk that a plurality of aggressor wires adjoining a victim wire inflict on said victim wire, the method comprising the steps of:

calculating a maximum value of delay degradation inflicted on said victim wire within a range of signal arrival time of each of said plurality of aggressor wires with reference to a signal arrival time on said victim wire for each of said aggressor wires,

adding results of tic step of calculating with reference to the signal arrival time on said victim wire, and

determining total delay degradation inflicted on said victim wire by crosstalk from said plurality of aggressor.

4. An electronic circuit device manufacturing method for manufacturing an electronic circuit device having the plurality of aggressor wires by using a crosstalk analysis method wherein a plurality of aggressor wires adjoining a victim wire inflict on said victim wire, the method comprising the steps of:

determining a delay degradation that each of said plurality of aggressor wires inflicts on said victim wire according to a range that can be taken by the respective dynamic signal arrival times on said victim wire and said plurality of aggressor wires, and

adding said delay degradations of said plurality of aggressor wires together with reference to the signal arrival time on said victim wire.

5. A delay time calculation method of an electronic circuit device for calculating a delay time in the electronic circuit device which is realized by using an automatic designing apparatus comprising a processing unit, a memory unit and a man-machine interface and in which there are a plurality of aggressor wires inflicting crosstalk on a victim wire and determining signal delay degradation values due to the crosstalk in the electronic circuit device, the method comprising the following steps which are executed with a program held on the memory:

(a) a step of inputting connection information on a logic circuit block or a logic circuit cell for determining logical relationship between a logical input and a logical output and physical space information on wiring used for the connection,

(b) a step of calculating, in figuring out a signal arrival time at at least one node in the logic circuit, a possible range of signal arrival at said at least one node,

(c) a step of extracting a wire belonging to a victim node in said at least one node at the step (b) and aggressor wires from the physical space information on wiring inputted at the step (a) in accordance with a prescribed condition,

(d) a step of calculating the delay degradation values at the victim node caused by the influence of said aggressor wires with use of the range of signal arrival time for the victim node obtained by executing the step (b), by executing the following substeps (d-1) through (d-4);

(d-1) a substep of holding the delay degradation values due to crosstalk with respect to combination of drivability of a drive circuit for said victim wire and drivability of a drive circuit for said aggressor wire extracted at the step (c) as a data form searchable at a relative time difference between signal arrival times of the victim node and the aggressor node,

(d-2) a substep of calculating a range of signal arrival time at the node to which the aggressor wire extracted at the step (c) belongs,

(d-3) a substep of converting the range of signal arrival time of the aggressor node calculated at the substep (d-2) into a range of relative signal arrival time with reference to the signal arrival time at the victim node, picking out a maximum one in the delay degradation values obtained at the substep (d-1) in the range of the relative signal arrival time, and holding it as a data form searchable at each signal arrival time at the victim node, and

(d-4) a substep of adding mutually the delay degradation values held at the substep (d-1) every signal arrival time at the victim node for the combination of said victim wire and said aggressor wires, and holding the resultant sum as a delay degradation value of each signal arrival time at the victim node.

6. A logic circuit designing system comprising a processing unit, a memory unit and a man-machine interface, the designing system being characterized in that delay degradation quantity has been reduced by, after a delay time is calculated for a plurality of aggressor wires inflicting crosstalk on a victim wire, determining signal delay degradation values due to the crosstalk in a logic circuit, identifying modified parts in the logic circuit in accordance with a prescribed condition, altering a configuration of the logic circuit, an arrangement of the modified parts or positions of wires, and thereby varying a signal arrival time.

7. An electronic circuit device designing method for designing an electronic circuit device having a plurality of aggressor wires adjoining a victim wire, the designing method comprising the steps of:

determining respective delay degradations that said plurality of aggressor wire inflict on said victim wire according to ranges that can be taken by respective dynamic signal arrival times at a node of said victim wire and node of said plurality of aggressor wires,

determining an overall delay degradation due to crosstalk that said plurality of aggressor wires inflict on said victim wire by integrating the delay degradations with reference to the signal arrival time on said victim wire thereby to calculate the total signal delay time at the node of said victim wire, and

designing the electronic circuit device on the basis of the result of this calculation.

8. An electronic circuit device designing method for designing an electronic circuit device having a plurality of aggressor wires adjoining a victim wire, the designing method comprising the steps of:

using a design tool having a screen on which a graphic image expressing characteristic of the respective delay degradations that said plurality of aggressor wires inflict on said victim wire with reference to a signal arrival time on said victim wire according to ranges that can be taken by respective signal arrival times at a node of said victim wire and nodes of said plurality of aggressor wires and another graphic image integrating the delay degradations with reference to the signal arrival time on said victim wire are displayed, and

analyzing characteristic of delay degradations due to crosstalk that said plurality of aggressor wires inflict on said victim wire node.

9. A recorded medium of an electronic circuit library, having stored in a computer-readable manner the electronic circuit library for use in calculating deploy degradation values due to a group of aggressor wires inflicting on a victim wire the electronic circuit library recording medium being characterized in that said library causes a computer to acquire delay degradation values according to differences between signal arrival times at nodes belonging to said aggressor wires and said victim wire in a case where there are a plurality of adjacent lengths of said aggressor wires and victim wire between which the crosstalk arises in regard to a combination of logical cells or logical blocks driving said victim wire and said aggressor wires and/or a combination of load drivability of the driving logical cells or the driving logical blocks.

10. A recorded medium of an electronic circuit library, having stored in a computer-readable manner the electronic circuit library for use in calculating delay degradation values due to a group of aggressor wires inflicting crosstalk on a victim wire the electronic circuit library recording medium being characterized in that said library causes a computer to acquire delay degradation values due to the crosstalk according to differences between signal arrival times at nodes belonging to said aggressor wires and said victim wire in regard to a combination of logical cells or logical blocks driving said victim wire and said aggressor wires and/or a combination of load drivability of the driving logical cells or the driving logical blocks, and acquire delay degradation values due to the crosstalk according to differences between signal arrival times at nodes belonging to said aggressor wires and said victim wire in a case where wiring is added to at least either of the closer side to and the farther side from the driving logical cells or driving logical blocks on a section where said victim wire and said aggressor wires are laid adjacent to each other.

11. An electronic circuit device manufacturing method for manufacturing an electronic circuit device having a plurality of aggressor wires by using the crosstalk calculation method wherein a second and a third aggressor wire inflict crosstalk on a first wire in the electronic circuit device, said second and said third aggressor wires being arranged adjacent to said first wire, said first wire being connected to an output section of a first electronic circuit unit, and said second and said third aggressor wires being connected to output sections of a second and a third electronic circuit unit respectively, the method comprising the steps of:

calculating a range of signal arrival time of each of said first wire and said second and said third aggressor wires on the basis of delay characteristics of signals in each of said first, said second and said third electronic circuit units,

determining delay degradation values due to crosstalk affecting said first wire according to timings of signals arriving on said second and said third wires on the basis or relative signal arrival times obtained by relative measuring of signal arrival times on said second and third wires with reference to a signal arrival time on said first wire, and

adding and said delay degradation values with reference to the signal arrival time on said first wire.

12. An electronic circuit device manufacturing method for manufacturing an electronic circuit device having a plurality of aggressor wires by using the crosstalk analysis method for analyzing signal crosstalk that the plurality of aggressor wires adjoining a victim wire inflict on said victim wire, the method comprising the steps of:

calculating a maximum value of delay degradation inflicted on said victim wire within a range of signal arrival time of each of said plurality of aggressor wires with reference to a signal arrival time on said victim wire for each of said aggressor wires,

adding results of the step of calculating with reference to the signal arrival time on said victim wire, and

determining total delay degradation inflicted on said victim wire by crosstalk from said plurality of aggressor wires.