Methods for improved metal gate fabrication

• US 6,773,978 B1
• Filed: 08/28/2002
• Issued: 08/10/2004
• Est. Priority Date: 07/23/2002
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pan, James, Paton, Eric, Besser, Paul Raymond
• Primary Examiner(s): Yevsikov, Victor V
• Application Number:
  US10/229,690
• Time in Patent Office: 713 Days
• Field of Search: 438/238, 438/257, 438/210, 438/275, 438/224, 438/229, 438/231, 438/286, 438/305, 438/346, 438/301, 257/407, 257/408, 257/757
• US Class Current: 438/238
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/28097 the final conductor layer next to the insulator being a metallic silicide
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Methods are disclosed for manufacturing semiconductor devices with silicide metal gates, wherein a single-step anneal is used to react a metal such as cobalt or nickel with substantially all of a polysilicon gate structure while source/drain regions are covered. A second phase conductive metal silicide is formed consuming substantially all of the polysilicon and providing a substantially uniform work function at the silicide/gate oxide interface.

Claims

1. A method of fabricating a transistor gate in a semiconductor device, comprising:

forming a gate oxide layer over a channel region of a substrate;

forming and pattering a polysilicon gate over the channel region, the polysilicon gate extending between a bottom surface overlying the gate oxide and a top surface;

forming a metal layer over the substrate, at least a portion of the metal layer overlying the top surface of the polysilicon gate, wherein the metal layer does not contact a source/drain region associated with the device; and

performing a single anneal to react the polysilicon with the portion of the metal layer to form a conductive second phase metal silicide gate extending from the bottom surface to the top surface,

wherein forming the metal layer comprises forming a cobalt layer overlying the top surface of the polysilicon gate, and

wherein forming the cobalt layer comprises depositing cobalt over the top surface of the polysilicon gate to a thickness of about 250 Å

or more and about 350 Å

or less, and wherein performing the anneal comprises performing the rapid thermal anneal at a temperature of about 700 degrees C. in an atmosphere comprising N₂ for about 10 seconds or more and about 60 seconds or less to provide a substantially uniform work function at the bottom surface of the gate, and

further comprising covering a portion of the substrate overlying at least one source/drain region prior to forming the cobalt layer to prevent silicidation of the covered portion of the substrate while performing the anneal.

2. The method of claim 1, further comprising removing unreacted metal after performing the anneal.

3. A method of fabricating a transistor gate in a semiconductor device, comprising:

forming a gate oxide layer over a channel region of a substrate;

forming and patterning a polysilicon gate over the channel region, the polysilicon gate extending between a bottom surface overlying the gate oxide and a top surface;

forming a metal layer over the substrate, at least a portion of the metal layer overlying the top surface of the polysilicon gate, wherein the metal layer does not contact a source/drain region associated with the device; and

performing a single anneal to react the polysilicon with the portion of the metal layer to form a conductive second phase metal silicide gate extending from the bottom surface to the top surface,

wherein forming the metal layer comprises forming a cobalt layer overlying the top surface of the polysilicon gate, and

wherein forming the cobalt layer comprises depositing cobalt over the top surface of the polysilicon gate to a thickness of about 250 Å

or more and about 350 Å

or less, and wherein performing the anneal comprises performing the rapid thermal anneal at a temperature of about 700 degrees C. in an atmosphere comprising N₂ for about 10 seconds or more and about 60 seconds or less to provide a substantially uniform work function at the bottom surface of the gate, and

further comprising forming a cap layer comprising one of Ti and TiN over the cobalt layer to getter oxygen while performing the rapid thermal anneal.

4. A method of fabricating a transistor gate in a semiconductor device, comprising:

forming a gate oxide layer over a channel region of a substrate;

forming and pattering a polysilicon gate over the channel region, the polysilicon gate extending between a bottom surface overlying the gate oxide and a top surface;

forming a metal layer over the substrate, at least a portion of the metal layer overlying the top surface of the polysilicon gate, wherein the metal layer does not contact a source/drain region associated with the device; and

performing a single anneal to react the polysilicon with the portion of the metal layer to form a conductive second phase metal silicide gate extending from the bottom surface to the top surface,

wherein forming the metal layer comprises forming a nickel layer overlying the top surface of the polysilicon gate, and wherein performing the anneal comprises performing a rapid thermal anneal at a temperature of about 500 degrees C. or more, and

wherein performing the anneal comprises reacting substantially all the polysilicon with the portion of the nickel layer to form the metal silicide gate comprising NiSi extending from the bottom surface to the top surface of the gate,

further comprising covering a portion of the substrate overlying at least one source/drain region prior to forming the nickel layer to prevent silicidation of the covered portion of the substrate while performing the anneal.

5. The method of claim 4, wherein forming the nickel layer comprises depositing nickel over the top surface of the polysilicon gate to a thickness of about 250 Å

or more and about 350 Å

or less, and wherein performing the anneal comprises performing the rapid thermal anneal in an atmosphere comprising N₂ for about 30 seconds or more and about 60 seconds or less to provide a substantially uniform work function at the bottom surface of the gate.