Thin film transistor array panel having a means for visual inspection

• US 6,774,398 B2
• Filed: 06/03/2002
• Issued: 08/10/2004
• Est. Priority Date: 10/11/2001
• Status: Expired due to Term

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Jin, Jang, Yong-Kyu, Lee, Won-Kyu
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US10/161,236
• Publication Number:
  US 20030075718A1
• Time in Patent Office: 799 Days
• Field of Search: 257/59, 257/72, 257/347, 349/42, 349/43
• US Class Current: 257/59
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate

Abstract

A plurality of gate lines and a plurality of data lines intersecting the gate lines to define a display area are formed on an insulating substrate including a display area and a surrounding area. On the surrounding area, a gate driving circuit connected to the gate lines and a logic circuit for VI interposed between the gate driving circuit and the gate line and having several first to third NOR gates are formed. A first input terminal of the first NOR gate of the logic circuit for VI is connected to an output terminal of the gate driving circuit, and a second input terminal thereof is connected to a CON1 terminal, and an output terminal thereof is connected to a first input terminal of the second or the third NOR gate. A second input terminal of the second NOR gate is connected to a CON2 terminal and an output terminal thereof is connected to the gate lines in odd number. A second input terminal of the NOR gate is connected to a CON3 terminal and an output terminal thereof is connected to the gate lines in even number.

Claims

1. A thin film transistor panel comprising:

an insulating substrate having a display area and a surrounding area;

a first signal line formed on the insulating substrate;

a second signal line formed on the insulating substrate and insulated with and intersecting the first signal line to define the display area;

a plurality of driving signal lines formed on the surrounding area of the insulating substrate and connected to a V_off voltage applying terminal;

a plurality of inspection signal lines formed on the surrounding area of the insulating substrate;

a first thin film transistor for inspection having a drain electrode coupled to the first signal line, a source electrode coupled to any one of the inspection signal lines and a gate electrode coupled to any one of the driving signal lines; and

a second thin film transistor for inspection having a drain electrode coupled to the second signal line, a source electrode coupled to any one of the inspection signal lutes and a gate electrode coupled to any one of the driving signal lines.

2. The thin film transistor panel of claim 1 wherein the driving signal lines connected to the second thin film transistor for inspection comprise first, second and third driving signal lines, and the second thin film transistor for inspection is connected to the first, the second and the third driving signal lines in turn.

3. The thin film transistor panel of claim 1, wherein the inspection signal line connected to the second thin film transistor for inspection comprises a first inspection signal line and a second inspection signal line, and the second thin film transistor for inspection are alternatingly connected to the first inspection signal line and the second inspection signal line.

4. The thin film transistor panel of claim 3, wherein the inspection signal line connected to the first thin film transistor for inspection comprises third and fourth inspection signal lines, and the first thin fun transistor for inspection is alternatingly connected to the thud inspection signal line and the fourth inspection signal line.

5. The thin film transistor panel of claim 1, wherein the inspection signal line connected to the second thin film transistor for inspection comprises first, second and third inspection signal lines, and the second thin film transistor for inspection is connected to the first, the second and the third inspection signal lines in turn.

6. The thin film transistor panel of claim 5, wherein the inspection signal line connected to the first thin film transistor for inspection comprises fourth and fifth inspection signal lines, and the first thin film transistor for inspection is alternatingly connected to the fourth and the fifth inspection signal lines.