Flash cell with trench source-line connection

• US 6,774,426 B2
• Filed: 12/19/2000
• Issued: 08/10/2004
• Est. Priority Date: 12/19/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Abedifard, Ebrahim
• Primary Examiner(s): Tran, Thien F
• Application Number:
  US09/741,525
• Publication Number:
  US 20020074592A1
• Time in Patent Office: 1,330 Days
• Field of Search: 257/315, 257/316, 257/317, 257/321
• US Class Current: 257/315
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed at regular intervals across a memory array. Such floating-gate memory cells have their drain regions and source regions formed in a first semiconductor region having a first conductivity type. This first semiconductor region is separated from the underlying substrate by an interposing second semiconductor region having a second conductivity type different from the first conductivity type. The source regions of the memory cells are coupled to the second semiconductor region as a common source line. Such memory cells can be programmed, read and erased by applying various potential levels to their control gates, their drain regions, the first semiconductor region, and the second semiconductor region.

Claims

1. A floating-gate memory cell, comprising:

a gate stack having a control-gate layer and having a floating-gate layer interposed between the control-gate layer and a first semiconductor region having a first conductivity type;

a drain region in the first semiconductor region, wherein the drain region has a second conductivity type different from the first conductivity type; and

a source region in the first semiconductor region and having the second conductivity type;

wherein the source region is coupled to a second semiconductor region underlying the first semiconductor region;

wherein the drain region is isolated from the second semiconductor region;

wherein the second semiconductor region has the second conductivity type; and

wherein the second semiconductor region isolates the first semiconductor region from other semiconductor regions having the first conductivity type.

2. The floating-gate memory cell of claim 1, wherein the first conductivity type is a p-type conductivity and the second conductivity type is an n-type conductivity.

3. The floating-gate memory cell of claim 1, wherein the source region is coupled to the second semiconductor region through a conductive source-line contact.

4. The floating-gate memory cell of claim 3, wherein the source-line contact comprises a columnar trench of conductive fill material.

5. The floating-gate memory cell of claim 3, wherein the source-line contact comprises an extended trench of conductive fill material and wherein the extended trench of conductive fill material is coupled to source regions of other floating-gate memory cells.

6. The floating-gate memory cell of claim 3, wherein the source-line contact comprises a conductive fill material formed on sidewalls and a bottom of a contact hole and wherein the sidewalls of the contact hole are defined by the first semiconductor region and the bottom of the contact hole is defined by an exposed portion of the second semiconductor region.

7. The floating-gate memory cell of claim 3, wherein the source-line contact comprises a conductive material and wherein the conductive material includes at least one material selected from the group consisting of an implanted conductively-doped region having the second conductivity type, a diffused conductively-doped region having the second conductivity type, conductively-doped polysilicon having the second conductivity type, a silicide, a polycide, a metal, a metal alloy, and a conductive metal oxide.

8. The floating-gate memory cell of claim 3, further comprising a conductive trace coupled between the source region and the source-line contact.

9. The floating-gate memory cell of claim 8, wherein the conductive trace is formed on the first semiconductor region.

10. The floating-gate memory cell of claim 8, wherein the conductive trace is formed in the first semiconductor region.

11. The floating-gate memory cell of claim 10, wherein the conductive trace is a conductively-doped region formed in the first semiconductor region and having the second conductivity type.

12. The floating-gate memory cell of claim 10, wherein the conductive trace contains a metal silicide.

13. A floating-gate memory cell, comprising:

a gate stack having a control-gate layer and having a floating-gate layer interposed between the control-gate layer and a first semiconductor region having a first conductivity type;

a drain region in the first semiconductor region, wherein the drain region has a second conductivity type different from the first conductivity type; and

a source region in the first semiconductor region and having the second conductivity type;

wherein the first semiconductor region is enclosed in a second semiconductor region having the second conductivity type; and

wherein the source region is coupled to the second semiconductor region and the drain region is isolated from the second semiconductor region.

14. A floating-gate memory cell, comprising:

a gate stack having a control-gate layer and having a floating-gate layer, wherein the gate stack is overlying an upper well region and wherein the upper well region has a first conductivity type;

a drain region in the upper well region, wherein the drain region has a second conductivity type different from the first conductivity type;

a source region in the upper well region and having the second conductivity type; and

a source-line contact extending from the source region to a lower well region;

wherein the lower well region has the second conductivity type;

wherein the upper well region is formed in the lower well region; and

wherein the drain region is not connected to the lower well region.

15. A floating-gate memory cell, comprising:

a tunnel dielectric layer overlying an upper well region, wherein the upper well region has a first conductivity type;

a floating-gate layer overlying the tunnel dielectric layer;

an intergate dielectric layer overlying the floating-gate layer;

a control-gate layer overlying the intergate dielectric layer;

a drain region in the upper well region, wherein the drain region has a second conductivity type different from the first conductivity type; and

a source region in the upper well region and having the second conductivity type, wherein the source region is coupled to a lower well region underlying the upper well region and having the second conductivity type;

wherein the lower well region is adapted to function as a source line.

16. The floating-gate memory cell of claim 15, wherein the tunnel dielectric layer is overlying and in contact with the upper well region, wherein the floating-gate layer is overlying and in contact with the tunnel dielectric layer, wherein the intergate dielectric layer is overlying and in contact with the floating-gate layer, and wherein the control-gate layer is overlying and in contact with the intergate dielectric layer.

17. The floating-gate memory cell of claim 15, wherein the source region is coupled to the lower well region through a conductive source-line contact.

18. The floating-gate memory cell of claim 17, further comprising a conductive trace coupled between the source region and the conductive source-line contact.

19. The floating-gate memory cell of claim 17, wherein the source-line contact comprises an extended trench of conductive fill material and wherein the extended trench of conductive fill material is coupled to source regions of other floating-gate memory cells.

20. The floating-gate memory cell of claim 17, wherein the source-line contact comprises a conductive fill material formed on sidewalls and a bottom of a contact hole and wherein the sidewalls of the contact hole are defined by the upper well region and the bottom of the contact hole is defined by an exposed portion of the lower well region.

21. The floating-gate memory cell of claim 17, wherein the source-line contact comprises a conductive material and wherein the conductive material includes at least one material selected from the group consisting of an implanted conductively-doped region having the second conductivity type, a diffused conductively-doped region having the second conductivity type, conductively-doped polysilicon having the second conductivity type, a silicide, a polycide, a metal, a metal alloy, and a conductive metal oxide.

22. The floating-gate memory cell of claim 17, wherein the source-line contact comprises a columnar trench of conductive fill material.

23. The floating-gate memory cell of claim 22, wherein the source-line contact is coupled to source regions of other floating-gate memory cells.

24. A memory device, comprising:

a substrate having a first conductivity type;

a lower well region in the substrate, wherein the lower well region has a second conductivity type different from the first conductivity type;

an upper well region in the lower well region, wherein the upper well region has the first conductivity type;

a plurality of word lines;

a plurality of bit lines; and

a plurality of floating-gate memory cells, wherein each floating-gate memory cell comprises;

a control-gate layer for coupling to one of the plurality of word lines;

a floating-gate layer interposed between the control-gate layer and the upper well region;

a drain region in the upper well region for coupling to one of the plurality of bit lines, wherein the drain region has the second conductivity type;

a source region in the upper well region, wherein the source region has the second conductivity type; and

a source-line contact extending below the source region to the lower well region and providing electrical communication between the source region and the lower well region;

wherein the lower well region functions as a common source line for the plurality of floating-gate memory cells.

25. The memory device of claim 24, wherein each floating-gate memory cell having a control-gate layer coupled to the same word line also shares the same source-line contact.

26. The memory device of claim 24, wherein each source-line contact is laterally displaced from each source region and wherein each source-line contact is coupled to at least one source region.

27. The memory device of claim 26, wherein each source-line contact is coupled to the at least one source region through a conductive trace.

28. The memory device of claim 24, wherein each source-line contact extends through at least one source region.

29. The memory device of claim 28, wherein each source-line contact extends through only one source region.

30. A memory device, comprising:

a substrate having a first conductivity type;

a lower well region in the substrate, wherein the lower well region has a second conductivity type different from the first conductivity type;

an upper well region in the lower well region, wherein the upper well region has the first conductivity type;

a plurality of word lines;

a plurality of bit lines; and

a plurality of floating-gate memory cells, wherein each floating-gate memory cell comprises;

a control-gate layer for coupling to one of the plurality of word lines;

a floating-gate layer interposed between the control-gate layer and the upper well region;

a drain region in the upper well region for coupling to one of the plurality of bit lines, wherein the drain region has the second conductivity type and is isolated from the lower well region;

a source region in the upper well region, wherein the source region has the second conductivity type; and

a source-line contact extending from the source region to the lower well region.

31. A memory device, comprising:

a substrate having a first conductivity type;

a first well region, wherein the first well region has the first conductivity type;

a second well region interposed between the substrate and the first well region, wherein the second well region has a second conductivity type different from the first conductivity type;

a plurality of word lines;

a plurality of bit lines; and

a plurality of floating-gate memory cells, wherein each floating-gate memory cell comprises;

a control-gate layer for coupling to one of the plurality of word lines;

a floating-gate layer interposed between the control-gate layer and the first well region;

a drain region in the first well region for coupling to one of the plurality of bit lines, wherein the drain region has the second conductivity type;

a source region in the first well region, wherein the source region has the second conductivity type; and

a source-line contact extending below the source region to the second well region and providing electrical communication between the source region and the second well region;

wherein the second well region is not in electrical communication with the drain region.

32. A memory device, comprising:

a substrate having a first conductivity type;

a first well region, wherein the first well region has the first conductivity type;

a second well region interposed between the substrate and the first well region, wherein the second well region has a second conductivity type different from the first conductivity type;

a third well region, wherein the third well region has the first conductivity type and wherein the third well region is isolated from the first well region;

a fourth well region interposed between the substrate and the third well region, wherein the fourth well region has the second conductivity type;

a first plurality of word lines;

a second plurality of word lines;

a plurality of bit lines;

a first block of floating-gate memory cells of a memory array, wherein each floating-gate memory cell of the first block of floating-gate memory cells comprises;

a control-gate layer for coupling to one of the first plurality of word lines;

a floating-gate layer interposed between the control-gate layer and the first well region;

a drain region in the first well region for coupling to one of the plurality of bit lines, wherein the drain region has the second conductivity type;

a source region in the first well region, wherein the source region has the second conductivity type; and

a source-line contact extending below the source region to the second well region and providing electrical communication between the source region and the second well region; and

a second block of floating-gate memory cells of the memory array, wherein each floating-gate memory cell of the second block of floating-gate memory cells comprises;

a control-gate layer for coupling to one of the second plurality of word lines;

a floating-gate layer interposed between the control-gate layer and the third well region;

a drain region in the third well region for coupling to one of the plurality of bit lines, wherein the drain region has the second conductivity type;

a source region in the third well region, wherein the source region has the second conductivity type; and

a source-line contact extending below the source region to the fourth well region and providing electrical communication between the source region and the fourth well region;

wherein the second well region is adapted to function as a common source line to the first block of floating-gate memory cells and the fourth well region is adapted to function as a common source line to the second block of floating-gate memory cells.

33. The memory device of claim 32, wherein the second well region and the fourth well region are the same well region.

34. The memory device of claim 32, wherein each control-gate layer coupled to each word line of the first plurality of word lines is associated with a floating-gate memory cell of the first block of floating-gate memory cells.

35. The memory device of claim 32, wherein each floating-gate memory cell having a control-gate layer coupled to the same word line also shares the same source-line contact.

36. The memory device claim 32, wherein each source-line contact is laterally displaced from each source region and wherein each source-line contact is coupled to at least one source region.

37. The memory device of claim 36, wherein each source-line contact is coupled to the at least one source region through a conductive trace.

38. The memory device of claim 32, wherein each source-line contact extends through at least one source region.

39. The memory device of claim 38, wherein each source-line contact extends through only one source region.

40. A floating-gate memory cell, comprising:

a gate stack having a control-gate layer and having a floating-gate layer interposed between the control-gate layer and a well region having a first conductivity type, wherein the well region having the first conductivity type is isolated from a semiconductor substrate having the first conductivity type by an interposing well region having a second conductivity type different from the first conductivity type;

a first source/drain region having the second conductivity type in the well region having the first conductivity type, wherein the first source/drain region is not coupled to the well region having the second conductivity type; and

a second source/drain region having the second conductivity type in the well region having the first conductivity type, wherein the second source/drain region is coupled to the well region having the second conductivity type.

41. The floating-gate memory cell of claim 40, wherein the well region having the first conductivity type is a p-well and wherein the interposing well region having the second conductivity type is an n-well in a p-type semiconductor substrate.

42. The floating-gate memory cell of claim 40, wherein the well region having the first conductivity type is an n-well and wherein the interposing well region having the second conductivity type is a p-well in an n-type semiconductor substrate.

43. A floating-gate memory cell, comprising:

a gate stack having a control-gate layer and having a floating-gate layer interposed between the control-gate layer and a p-well, wherein the p-well is enclosed in an n-well formed in a p-type semiconductor substrate;

a drain region in the p-well, wherein the drain region has an n⁺-type conductivity, wherein the drain region is isolated from the n-well; and

a source region in the p-well and having the n⁺-type conductivity, wherein the source region is coupled to the n-well.

44. A floating-gate memory cell, comprising:

a gate stack having a control-gate layer and having a floating-gate layer, wherein the gate stack is overlying a p-well and wherein the p-well is enclosed in an n-well formed in a p-type semiconductor substrate;

an n⁺-type drain region in the p-well;

an n⁺-type source region in the p-well; and

a source-line contact coupled to the n⁺-type source region and extending below the n⁺-type source region to the n-well;

wherein the n-well serves as a source line to the floating-gate memory cell.

45. A floating-gate memory cell, comprising:

a gate stack having a control-gate layer and having a floating-gate layer, wherein the gate stack is overlying a p-well and wherein the p-well is enclosed in an n-well formed in a p-type semiconductor substrate;

an n⁺-type drain region in the p-well and isolated from the n-well;

an n⁺-type source region in the p-well; and

a source-line contact extending from the n⁺-type source region to the n-well.

46. The floating-gate memory cell of claim 45, wherein the source-line contact extends from multiple n⁺type source regions to the n-well.

47. The floating-gate memory cell of claim 45, wherein the source-line contact extends from only one n⁺-type source region to the n-well.

48. A floating-gate memory cell, comprising:

a tunnel dielectric layer overlying an upper well region, wherein the upper well region has a p-type conductivity;

a floating-gate layer overlying the tunnel dielectric layer;

an intergate dielectric layer overlying the floating-gate layer;

a control-gate layer overlying the intergate dielectric layer;

a drain region in the upper well region, wherein the drain region has an n⁺-type conductivity; and

a source region in the upper well region and having the n⁺-type conductivity, wherein the source region is coupled to a lower well region underlying the upper well region;

wherein the lower well region has an n-type conductivity;

wherein the lower well region is formed in a semiconductor substrate having the p-type conductivity; and

wherein the lower well region is adapted to function as source line to the floating-gate memory cell.

49. The floating-gate memory cell of claim 48, wherein the source region is coupled to the lower well region through a source-line contact as an extended trench of conductive fill material and wherein the extended trench of conductive fill material is coupled to source regions of other floating-gate memory cells.

50. The floating-gate memory cell of claim 48, wherein the source region is coupled to the lower well region through a source-line contact as a columnar trench of conductive fill material.

51. The floating-gate memory cell of claim 50, further comprising a conductive trace coupled between the source region and the source-line contact.

52. A memory device, comprising:

a substrate having a p-type conductivity;

a lower well region formed in the substrate, wherein the lower well region has an n-type conductivity;

an upper well region formed in the lower well region, wherein the upper well region has the p-type conductivity;

a plurality of word lines;

a plurality of bit lines; and

a plurality of floating-gate memory cells, wherein each floating-gate memory cell comprises;

a control-gate layer for coupling to one of the plurality of word lines;

a floating-gate layer interposed between the control-gate layer and the upper well region;

a drain region in the upper well region for coupling to one of the plurality of bit lines, wherein the drain region has an n⁺-type conductivity and is isolated from the lower well region;

a source region in the upper well region, wherein the source region has the n⁺-type conductivity; and

a source-line contact extending below the source region to the lower well region, wherein the source-line contact is coupled to the source region.

53. The memory device of claim 52, wherein each floating-gate memory cell having a control-gate layer coupled to the same word line also shares the same source-line contact.

54. The memory device of claim 52, wherein each source-line contact is laterally displaced from each source region and wherein each source-line contact is coupled to at least one source region.

55. The memory device of claim 54, wherein each source-line contact is coupled to the at least one source region through a conductive trace.

56. The memory device of claim 52, wherein each source-line contact extends through at least one source region.

57. The memory device of claim 56, wherein each source-line contact extends through only one source region.

58. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device includes an array of floating-gate memory cells arranged in rows and columns with word lines coupled to rows of floating-gale memory cells and bit lines coupled to columns of floating-gate memory cells, and wherein at least one of the floating-gate memory cells comprises;

a gate stack having a control-gate layer coupled to a word line and having a floating-gate layer interposed between the control-gate layer and a first semiconductor region having a first conductivity type;

a drain region in the first semiconductor region coupled to a bit line, wherein the drain region has a second conductivity type different from the first conductivity type; and

a source region in the first semiconductor region and having the second conductivity type;

wherein the source region is coupled to a second semiconductor region underlying the first semiconductor region and the drain region is isolated from the second semiconductor region;

wherein the second semiconductor region has the second conductivity type; and

wherein the second semiconductor region isolates the first semiconductor region from other semiconductor regions having the first conductivity type.

59. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, wherein the memory device comprises;

a substrate having a first conductivity type;

a lower well region in the substrate, wherein the lower well region has a second conductivity type different from the first conductivity type;

an upper well region in the lower well region, wherein the upper well region has the first conductivity type;

a plurality of word lines;

a plurality of bit lines;

an array of floating-gate memory cells, wherein each floating-gate memory cell comprises;

a control-gate layer for coupling to one of the plurality of word lines;

a floating-gate layer interposed between the control-gate layer and the upper well region;

a drain region in the upper well region for coupling to one of the plurality of bit lines, wherein the drain region has the second conductivity type;

a source region in the upper well region, wherein the source region has the second conductivity type; and

a source-line contact extending below the source region to the lower well region, wherein the source-line contact is coupled to the source region; and

a plurality of data lines coupled between the array of floating-gate memory cells and the processor;

wherein the lower well region is adapted to function as a common source line to the array of floating-gate memory cells.