Semiconductor device having an MIS transistor

• US 6,774,441 B2
• Filed: 01/13/2003
• Issued: 08/10/2004
• Est. Priority Date: 08/08/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Ishigaki, Yoshiyuki, Fujii, Yasuhiro, Maki, Yukio
• Primary Examiner(s): Wilson, Allan R.
• Application Number:
  US10/340,731
• Publication Number:
  US 20040026747A1
• Time in Patent Office: 575 Days
• Field of Search: 257/377, 257/382, 257/384, 257/388, 257/401
• US Class Current: 257/384
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823443 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers

Abstract

A semiconductor device according to the present invention includes a silicon substrate having a main surface, a gate electrode provided on the main surface of the silicon substrate, a first sidewall insulating film provided to cover a side surface of the gate electrode and including two layers of an oxide sidewall film as an underlay and a nitride sidewall film, a second sidewall insulating film provided to cover a surface of the first sidewall insulating film, and a cobalt silicide layer arranged above source and drain regions and at a position farther than the second sidewall insulating film from the gate electrode. The second sidewall insulating film fills in a removed portion located at a lower end of the oxide sidewall film. This allows a semiconductor device formed by employing a salicide process to prevent increase of leak current caused by a metal silicide layer.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a main surface;

a gate electrode provided on a main surface of said semiconductor substrate with an insulating film interposed;

a first sidewall insulating film having two layers;

a first layer of silicon oxide on a side surface of said gate electrode and having a lower portion extending on the main surface of said semiconductor substrate; and

a second layer of silicon nitride on said silicon oxide film and having a lower surface over the lower portion of the first layer of silicon oxide;

a second sidewall insulating film provided to cover a surface of said first sidewall insulating film and having a lower part extending under the lower surface of the second layer of silicon nitride to fill in a removed portion of said silicon oxide film;

source and drain regions provided at positions on a main surface of said semiconductor substrate where said gate electrode is arranged in between; and

a metal silicide layer arranged above said source and drain regions and at a position farther than said second sidewall insulating film from said gate electrode.

2. The semiconductor device according to claim 1, wherein said second sidewall insulating film is a silicon nitride film.

3. The semiconductor device according to claim 1, wherein

said source and drain regions include

a first diffusion region formed to have a first depth from the main surface of said semiconductor substrate, using said gate electrode as a mask, and

a second diffusion region formed to have a second depth greater than said first depth, using said first sidewall insulating film as a mask.

4. The semiconductor device according to claim 3, wherein

said source and drain regions further include a third diffusion region arranged below a middle portion of said metal silicide layer and formed to have a third depth larger than said second depth, using said second sidewall insulating film as a mask.

5. A semiconductor device, comprising:

a semiconductor substrate having a main surface;

a gate electrode provided on the main surface of said semiconductor substrate with an insulating film interposed;

source and drain regions provided at positions on the main surface of said semiconductor substrate where said gate electrode is arranged in between; and

a metal silicide layer arranged above said source and drain regions,

said source and drain regions including a first lightly doped diffusion region formed to have a first depth from the main surface of said semiconductor substrate, a second heavily doped diffusion region formed to have a second depth greater than said first depth, and a third heavily doped diffusion region arranged below a middle portion of said metal silicide layer and formed to have a third depth greater than said second depth, wherein;

said first, second and third diffusion regions are formed of the same conductivity type.

6. The semiconductor device according to claim 5, further comprising:

a first sidewall insulating film provided to cover a side surface of said gate electrode; and

a second sidewall insulating film provided to cover a surface of said first sidewall insulating film,

said first diffusion region being formed using said gate electrode as a mask, said second diffusion region being formed using said first sidewall insulating film as a mask, said third diffusion region being formed using said second sidewall insulating film as a mask.

7. The semiconductor device according to claim 6, wherein said second sidewall insulating film is formed by an atmospheric CVD method.