Semiconductor device

• US 6,774,674 B2
• Filed: 07/17/2002
• Issued: 08/10/2004
• Est. Priority Date: 07/19/2001
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Okamoto, Kazuaki, Araki, Toru
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/196,228
• Publication Number:
  US 20030016054A1
• Time in Patent Office: 755 Days
• Field of Search: 326/79, 326/68, 326/63, 326/62, 326/80, 326/87, 327/112, 327/311, 327/381, 327/388, 327/427
• US Class Current: 326/80
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/08128 in composite switches
• CPC Class Codes: H03K 17/107 in composite switches

Abstract

A high-potential side power device driving circuit has a clock signal generation circuit generating the so-called internal clock signal by outputting a pulse in a constant cycle for driving NMOS transistors and an iterative pulse generation circuit monitoring the state of an external input signal in synchronization with an output signal of the clock signal generation circuit, receiving a pulsing input signal generated with reference to a ground potential and generating pulsing ON and OFF signals. Thus provided is a level shifting circuit capable of preventing a power device from a malfunction also when a dv/dt transient signal is supplied with time difference.

Claims

1. A semiconductor device driving/controlling first and second switching devices serially connected with each other and interposed between a high main power supply potential and a low main power supply potential, comprising:

a control part controlling conduction/non-conduction of a high-potential side switching device of either said first or second switching device;

a pulse generation part generating first and second iterative pulse signals in correspondence to first and second states of a first input signal having said first state indicating conduction of said high-potential side switching device and said second state indicating non-conduction of said high-potential side switching device, and said pulse generation part generates one of said first iterative pulse signal and said second iterative pulse signal only when the other of said first iterative pulse signal and said second iterative pulse signal is not generated; and

a level shifting part level-shifting said first and second iterative pulse signals to a higher potential side for obtaining first and second level-shifted iterative pulse signals respectively, wherein

said control part outputs a control signal rendering said high-potential side switching device conductive or non-conductive on the basis of said first and second level-shifted iterative pulse signals.

2. The semiconductor device according to claim 1, wherein said pulse generation part comprises:

a clock signal generation part generating a clock signal, and

an iterative pulse generation part receiving said clock signal and said first input signal and outputting said clock signal as said first iterative pulse signal only in a period when said first input signal is in said first state while outputting said clock signal as said second iterative pulse signal only in a period when said first input signal is in said second state.

3. The semiconductor device according to claim 2, further comprising:

a logic circuit receiving said first and second level-shifted iterative pulse signals, operating the OR of said signals for reproducing said clock signal or an external clock signal and outputting the same as an internal clock signal.

4. The semiconductor device according to claim 2, wherein

a second input signal controls conduction/non-conduction of a low-potential side switching device of either said first or second switching device,

said semiconductor device further comprising:

a synchronous circuit receiving said clock signal or an external clock signal and said second input signal and outputting said second input signal as a synchronous control signal in synchronization with said clock signal or said external clock signal, for controlling conduction/non-conduction of said low-potential side switching device by said synchronous control signal.

5. The semiconductor device according to claim 1, wherein said pulse generation part comprises:

an iterative pulse generation part receiving an external clock signal and said first input signal and outputting said external clock signal as said first iterative pulse signal only in a period when said first input signal is in said first state while outputting said external clock signal as said second iterative signal only in a period when said first input signal is in said second state, and

said first input signal is synchronous with said external clock signal.

6. The semiconductor device according to claim 5, further comprising:

a logic circuit receiving said first and second level-shifted iterative pulse signals, operating an OR of said signals for reproducing said clock signal or said external clock signal and outputting the same as an internal clock signal.

7. The semiconductor device according to claim 5, wherein

a second input signal controls conduction/non-conduction of a low-potential side switching device of either said first or second switching device,

said semiconductor device further comprising:

a synchronous circuit receiving said clock signal or said external clock signal and said second input signal and outputting said second input signal as a synchronous control signal in synchronization with said clock signal or said external clock signal, for controlling conduction/non-conduction of said low-potential side switching device by said synchronous control signal.

8. The semiconductor device according to claim 1, wherein

said pulse generation part comprises:

a first oscillation circuit receiving said first input signal and outputting said first iterative pulse signal in synchronization with transition of said first input signal to said first state only in a period when said first input signal is in said first state, and

a second oscillation circuit receiving said first input signal and outputting said second iterative pulse signal in synchronization with transition of said first input signal to said second state only in a period when said first input signal is in said second state.

9. The semiconductor device according to claim 1, wherein said pulse generation part comprises:

a clock signal generation part generating a clock signal,

an iterative pulse generation part receiving said clock signal and said first input signal and outputting said clock signal as a first signal only in a period when said first input signal is in said first state while outputting said clock signal as a second signal only in a period when said first input signal is in said second state,

a first one-shot pulse generation circuit receiving said first input signal and outputting a third signal having a pulse synchronized with transition of said first input signal to said first state in each cycle of said first input signal,

a second one-shot pulse generation circuit receiving an inverted signal of said first input signal and outputting a fourth signal having a pulse synchronized with transition of said first input signal to said second state in each cycle of said first input signal,

a first logic circuit receiving said first and third signals, operating a first OR of said signals and outputting the same as said first iterative pulse signal, and

a second logic circuit receiving said second and fourth signals, operating a second OR of said signals and outputting the same as said second iterative signal.

10. The semiconductor device according to claim 1, wherein said pulse generation part comprises:

a clock signal generation part generating a clock signal,

an iterative pulse generation part receiving said clock signal and said first input signal and outputting said clock signal as a first signal only in a period when said first input signal is in said first state while outputting said clock signal as a second signal only in a period when said first input signal is in said second state,

a latch circuit receiving said clock signal and said first input signal and having a first output end set in synchronization with transition of said first input signal to said first state and a second output end set in synchronization with transition of said first input signal to said second state while said first and second output ends are reset in synchronization with said clock signal,

a first logic circuit receiving said first signal and a third signal output from said first output end, operating a first OR of said signals and outputting the same as said first iterative pulse signal, and

a second logic circuit receiving said second signal and a fourth signal output from said second output end, operating a second OR of said signals and outputting the same as said second iterative pulse signal.

11. The semiconductor device according to claim 1, wherein

said pulse generation part comprises:

a clock signal generation part generating a clock signal,

an iterative pulse generation part receiving said clock signal and said first input signal and outputting said clock signal as a first signal only in a period when said first input signal is in said first state while outputting said clock signal as a second signal only in a period when said first input signal is in said second state,

a latch circuit receiving said clock signal and said first input signal and having a first output end set in synchronization with transition of said first input signal to said first state and a second output end set in synchronization with transition of said first input signal to said second state while said first and second output ends are reset in synchronization with said clock signal,

a first logic circuit receiving said first signal and a third signal output from said first output end, operating a first OR of said signals and outputting the same as a fifth signal,

a second logic circuit receiving said second signal and a fourth signal output from said second output end, operating a second OR of said signals and outputting the same as a sixth signal,

a first one-shot pulse generation circuit receiving said fifth signal, reducing a first duty ratio of a pulse included in said fifth signal and outputting the same as said first iterative pulse signal, and

a second one-shot pulse generation circuit receiving said sixth signal, reducing a second duty ratio of a pulse included in said sixth signal and outputting the same as said second iterative pulse signal.

12. The semiconductor device according to claim 1, further comprising clock signal adjusting means performing prescribed processing on said clock signal so that said first and second iterative pulse signals are not generated in proximity to each other in excess of a prescribed interval.

13. The semiconductor device according to claim 12, further comprising a filter circuit arranged on a front stage of said control part, wherein

said filter circuit supplies a prescribed signal to said control part to continuously output immediately preceding said control signal in a period when said first and second level-shifted iterative pulse signals are simultaneously input.

14. The semiconductor device according to claim 1, further comprising a filter circuit arranged on a front stage of said control part, wherein

said filter circuit supplies a prescribed signal to said control part to continuously output immediately preceding said control signal in a period when said first and second level-shifted iterative pulse signals are simultaneously input.

15. The semiconductor device according to claim 9, further comprising clock signal adjusting means performing prescribed processing on said clock signal so that said first and second iterative pulse signals are not generated in proximity to each other in excess of a prescribed interval.

16. The semiconductor device according to claim 15, wherein said clock signal adjusting means includes:

a delay circuit receiving said first input signal, supplying a prescribed delay for forming a delayed input signal and supplying the same to at least said iterative pulse generation part and said first and second one-shot pulse generation circuits in place of said first input signal, and

a mask circuit receiving said clock signal and masking valid said clock signal by a prescribed period corresponding to the period of said prescribed delay on the basis of said first input signal and said delayed input signal for supplying the same to said iterative pulse generation part as a mask signal.

17. The semiconductor device according to claim 15, wherein

said clock signal adjusting means includes a delay circuit receiving said first input signal, supplying a prescribed delay for forming a delayed input signal and supplying the same to said iterative pulse generation part and said first and second one-shot pulse generation circuits, and

said iterative pulse generation part receives said clock signal, said first input signal and said delayed input signal and separates the intervals for generating said first and second iterative pulse signals by said prescribed period.

18. The semiconductor device according to claim 9, further comprising a filter circuit arranged on a front stage of said control part, wherein

said filter circuit supplies a prescribed signal to said control part to continuously output immediately preceding said control signal in a period when said first and second level-shifted iterative pulse signals are simultaneously input.

19. The semiconductor device according to claim 1, further comprising pulse control means controlling said pulse generation part to generate said first and second iterative pulse signals only for a prescribed period from transition of said first input signal to said second state and from transition to said first state.

20. The semiconductor device according to claim 9, further comprising pulse control means controlling said pulse generation part to generate said first and second iterative pulse signals only for a prescribed period from transition of said first input signal to said second state and from transition to said first state.