Differential cascode current mode driver

• US 6,774,678 B2
• Filed: 02/14/2003
• Issued: 08/10/2004
• Est. Priority Date: 04/16/2001
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mooney, Stephen R., Martin, Aaron K.
• Primary Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US10/368,901
• Publication Number:
  US 20030122586A1
• Time in Patent Office: 543 Days
• Field of Search: 326/115, 326/127, 326/82, 326/86, 326/30, 327/51-55, 327/89
• US Class Current: 326/115
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0282 Provision for current-mode coupling
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling

Abstract

A current mode driver includes a tail current device, a differential pair of input transistors, cascode output transistors, and pre-charge circuits to charge cascode nodes between the differential pair of input transistors and the cascode output transistors. The current mode driver is driven by CMOS drivers that alternately turn the input transistors on and off. A wide-swing bias circuit provides bias voltages for the current mode driver. This bias voltage for the tail current device is closely matched to provide current matching between the bias circuit and the current mode driver.

Claims

1. A current mode driver circuit comprising:

a pair of differential output nodes;

a cascode output circuit coupled between the pair of differential output nodes and a pair of internal cascode nodes; and

a pair of pre-charge circuits, each pre-charge circuit to pre-charge one of the internal cascode nodes to approximately a bias voltage when current is flowing through an opposite of the internal cascade nodes.

2. The current mode driver of claim 1

wherein the internal cascade nodes receive a differential input signal from a differential pair of input transistors; and

wherein each of the pre-charge circuits receives a control input from an input of an opposite one of transistors of the differential pair of input transistors, the precharge circuits responsive to the control input by pre-charging one of the internal cascode nodes to approximately the bias voltage.

3. An integrated circuit comprising:

a differential receiver having first and second differential input node pairs;

a first current mode driver having an input node coupled to an outbound data node, and a differential output node pair coupled to the first differential input node pair of the differential receiver; and

a second current mode driver having an input node coupled to the outbound data node, a differential output node pair coupled to the second differential input node pair of the differential receiver,

wherein the current mode drivers comprise;

a pair of differential output nodes;

a cascade output circuit coupled between the pair of differential output nodes and a pair of internal cascode nodes; and

a pair of pre-charge circuits, each pre-charge circuit to pre-charge one of the internal cascade nodes to approximately a bias voltage when current is flowing through an opposite of the internal cascade nodes.

4. The integrated circuit of claim 3

wherein the internal cascade nodes receive a differential input signal from a differential pair of input transistors; and

wherein each of the pre-charge circuits receives a control input from an input of an opposite one of transistors of the differential pair of input transistors, the precharge circuits responsive to the control input by pre-charging one of the internal cascode nodes to approximately the bias voltage.