Memory architecture for micromirror cell
First Claim
1. A micromirror device comprising:
- a memory cell with a polysilicon-to-substrate storage capacitor, said memory cell comprising;
a single CMOS transistor having an inherent junction capacitor and electrically connected to said polysilicon-to-substrate storage capacitor;
a bit-line providing data to said memory cell;
a word address line; and
a mirror address node connected to an output of said memory cell;
a mirror superstructure electrically connected to said memory cell; and
reset electrodes positioned by said mirror superstructure.
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Abstract
A one transistor one capacitor micromirror with DRAM memory cell built around a large polysilicon-to-substrate capacitor which is not susceptible to recombination of photo-generated carriers caused by illumination in the projector. This large polysilicon-to-substrate capacitor overshadows the much smaller inherent parallel depletion capacitance which is sensitive to light. The device is further 100% shielded from exposed light by metal layers and the address node is located under the center of the micromirror mirror to obtain maximum shielding of light for the smaller, light sensitive, depletion portion of the capacitance. As a result the micromirror of this invention can adequately hold the cell charge in excess of the device load time of 300 μSec even in extremely high brightness projector applications. This invention also provides a feature which automatically forces micromirror mirrors located over bad CMOS memory cell to the dark state, which is much less objectionable in most applications, thereby improving the overall effective processing yield.
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Citations
15 Claims
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1. A micromirror device comprising:
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a memory cell with a polysilicon-to-substrate storage capacitor, said memory cell comprising;
a single CMOS transistor having an inherent junction capacitor and electrically connected to said polysilicon-to-substrate storage capacitor;
a bit-line providing data to said memory cell;
a word address line; and
a mirror address node connected to an output of said memory cell;
a mirror superstructure electrically connected to said memory cell; and
reset electrodes positioned by said mirror superstructure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A micromirror device comprising:
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a memory cell with a polysilicon-to-substrate storage capacitor;
a mirror superstructure electrically connected to said memory cell; and
an address layer comprising reset electrodes positioned by said mirror superstructure;
an oxide layer;
a hinge and yoke layer above said metal layer;
a mirror metal layer above said hinge and yoke layer; and
wherein said reset electrodes are formed on said oxide layer;
said reset electrodes comprising a “
reset” and
“
reset bar”
electrode, wherein;
said “
reset” and
“
reset bar”
electrode steady state values are set at +20 and −
15 volts, respectively;
said “
reset” and
“
reset bar”
electrodes are switched to −
15V and +20 volts, respectively, to reset the micromirror mirrors;
said “
reset” and
“
reset bar”
electrodes are switched to +5 volts and 0 volts, respectively, to set said mirrors to their new state;
the mirror is addressed at 0 volts to rotate said mirror −
10°
OFF, andsaid mirror is addressed at +5 volts to rotate said mirror +10°
ON.- View Dependent Claims (12, 13, 14, 15)
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Specification
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- Resources
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Current AssigneeTexas Instruments, Inc.
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Original AssigneeTexas Instruments, Inc.
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InventorsKnipe, Richard L., Huffman, James D., Hornbeck, Larry J.
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Primary Examiner(s)Yoha, Connie C.
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Application NumberUS10/034,896Publication NumberTime in Patent Office956 DaysField of Search365/149, 365/237, 365/106US Class Current365/149CPC Class CodesG02B 26/0841 the reflecting element bein...G11C 11/404 with one charge-transfer ga...G11C 13/04 using optical elements ; us...G11C 7/005 with combined beam-and indi...
