Semiconductor memory device having an array voltage control circuit constructed with a plurality of feedback loops

• US 6,775,199 B2
• Filed: 04/01/2003
• Issued: 08/10/2004
• Est. Priority Date: 06/08/2002
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Byung-Chul, Kim, Doo-Young
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): PHAM, LY D
• Application Number:
  US10/405,770
• Publication Number:
  US 20030227812A1
• Time in Patent Office: 497 Days
• Field of Search: 365/226, 365/214, 365/207, 365/189.09, 365/230.03
• US Class Current: 365/226
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

The invention discloses a semiconductor memory device having an array voltage control circuit constructed with a plurality of feedback loops. In order to maintain constant the array voltage used for a single memory cell array region the plurality of feedback loops dividedly connect to a power line structure covering the memory cell array region, resulting in a reduction in the load to be taken by the output of feedback amplifiers to thereby achieve stable array voltage control operations.

Claims

1. A semiconductor memory device, comprising:

a power supply mesh associated with a memory cell array;

a plurality of feedback circuits adapted to control supply of an array voltage to predetermined portions of the memory cell array through the power supply mesh;

where the power supply mesh includes a plurality of divisional liners, each divisional liner being associated with a particular portion of the memory cell array.

2. The semiconductor memory device of claim 1 where each feedback circuit comprises:

a feedback bus; and

a feedback amplifier adapted to compare an array reference voltage to an array voltage received from the feedback bus.

3. The semiconductor memory device of claim 1 including a plurality of voltage driver circuits, each voltage driver circuit being adapted to provide the array voltage to the predetermined portions of the memory cell array responsive to corresponding feedback circuits.

6. The semiconductor memory device of claim 1 where the power supply mesh is a single mesh.

4. A semiconductor memory device comprising:

a power supply mesh associated with a memory cell array; and

a plurality of feedback circuits adapted to control supply of an array voltage to predetermined portions of the memory cell array through the power supply mesh;

where the plurality of feedback circuits is capable of maintaining constant a level of the array voltage by providing the array voltage to the power supply mesh through a plurality of paths.

5. A semiconductor memory device comprising:

a power supply mesh associated with a memory cell array;

a plurality of feedback circuits adapted to control supply of an array voltage to predetermined portions of the memory cell array through the power supply mesh; and

a plurality of array voltage drivers adapted to supply the array voltage to the power supply mesh responsive to the plurality of feedback circuits.

7. A semiconductor memory device comprising:

a power supply mesh associated with a memory cell array; and

a plurality of feedback circuits adapted to control supply of an array voltage to predetermined portions of the memory cell array through the power supply mesh;

where the power supply mesh includes a plurality of divisional supply liners; and

where each of the plurality of feedback circuits is coupled to one of the divisional supply liners.