High-speed communication system with a feedback synchronization loop

• US 6,775,328 B1
• Filed: 08/11/1999
• Issued: 08/10/2004
• Est. Priority Date: 08/11/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Segaram, Para K.
• Primary Examiner(s): Phu, Phoung
• Application Number:
  US09/372,319
• Time in Patent Office: 1,826 Days
• Field of Search: 375/257, 375/258, 375/219, 375/220, 375/221, 375/222, 375/354, 375/356, 375/358, 710/52, 710/58, 710/61, 710/71
• US Class Current: 375/257
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

In a communications device having a physical layer device and a processing device connected to the physical layer device, the number of input/output (I/O) ports required for communication between the devices in the gigabit range is substantially reduced by utilizing millivolt differential I/O drivers and receivers. In addition, a calibration feedback loop synchronizes the data and clock signals on the processing device, thereby eliminating the need to recover the clock on the processing device.

Claims

1. A communication device comprising:

a physical layer device having;

a media driver connectable to a transmission medium;

a media receiver connectable to the transmission medium; and

a serializer/deserializer (serdes) connected to the media driver and the media receiver;

a master circuit connected to the serdes, the master circuit having;

a first physical layer data driver, the first physical layer data driver driving a millivolt differential signal; and

a first physical layer data receiver; and

a processing circuit having;

an internal circuit; and

a slave circuit connected to the internal circuit and the master circuit, the slave circuit having;

a first processing data receiver connected to the first physical layer data driver, the first processing data receiver outputting a first signal in response to receiving the signal output from the first physical layer data driver; and

a first processing data driver connected to the first physical layer data receiver, and connectable to the first processing data receiver.

2. The device of claim 1

wherein the master circuit further includes a clock driver connected to the serdes, the clock driver driving a millivolt differential signal;

wherein the slave circuit further includes a clock receiver connected to the clock driver, the clock receiver outputting a clock signal in response to a signal received from the clock driver; and

wherein the first processing data driver is connectable to receive the clock signal from the clock receiver or the first signal from the first processing data receiver, the first physical layer data receiver receiving the clock signal when the first processing data driver is connected to receive the clock signal, and the first signal when the first processing data driver is connected to receive the first signal.

3. The device of claim 2 wherein the master circuit further comprises an aligner connected to the first physical layer data receiver, the aligner receiving the clock signal when the first physical layer data receiver receives the clock signal, the aligner receiving the first signal when the first physical layer data receiver receives the first signal, the aligner having phase comparison circuitry that compares a phase of the clock signal received by the aligner with a phase of the first signal received by the aligner to determine a phase difference.

4. The device of claim 3 wherein the master circuit further comprises a phase delay circuit connected to the aligner, the serdes, and the first physical layer data driver, the aligner passing a plurality of signals to the phase delay circuit that indicates the phase difference, the phase delay circuit delaying the signal output from the first physical layer data driver so that the first signal received by the aligner is substantially in phase with the clock signal received by the aligner.

5. The device of claim 4 wherein the slave circuit further includes:

a first multiplexor connected to the clock input receiver and the first processing data receiver, the first multiplexor passing the clock signal output by the clock receiver when a first mux signal is in a first logic state, and passing the first signal output by the first processing data receiver when the first mux signal is in a second logic state; and

a second multiplexor connected to the first multiplexor and the first communication data driver, the second multiplexor passing a signal output from the first multiplexor when a second mux signal is in a first logic state, and passing an output data signal when the second mux signal is in a second logic state, the signal output from the first multiplexor being the clock signal when the first mux signal is in the first logic state, and being the first signal when the first mux signal is in the second logic state.

6. The device of claim 5 wherein the slave circuit further includes a serial-to-parallel shift register connected to the clock receiver, the first processing data receiver, and the internal circuit, the clock signal output by the clock receiver clocking the shift register.

7. The device of claim 5 wherein the slave circuit further includes a parallel-to-serial shift register connected to the internal circuit, the second multiplexor, and the clock receiver, the shift register outputting a data output signal in response to a parallel data signal from the internal circuit, the clock signal output by the clock receiver clocking the parallel-to-serial shift register.

8. The device of claim 7 wherein the slave circuit further includes a logic circuit connected to the first mux, the second mux, and the parallel-to-serial shift register, the logic circuit receiving the clock signal from the parallel-to-serial shift register, and setting the logic states of the first and second mux signals in response to commands extracted from the clock signal.

9. The device of claim 8 wherein the media receiver receives a signal from the transmission media having a first frequency, wherein the signal output from the serdes has a second frequency, and wherein the first frequency and the second frequency are substantially equivalent.

10. A processing circuit comprising:

an internal circuit; and

a slave circuit connected to the internal circuit, the slave circuit having;

a clock receiver connectable to a clock driver, the clock receiver outputting a clock signal in response to a millivolt differential signal received from the clock driver;

a first processing data receiver connectable to a first physical layer data driver, the first processing data receiver outputting a first signal in response to a millivolt differential signal received from the first physical layer data driver;

a first processing data driver connectable to a first physical layer data receiver, the first processing data driver being connectable to receive the clock signal from the clock receiver or the first signal from the first processing data receiver.

11. The circuit of claim 10 wherein the slave circuit further comprises:

a first multiplexor connected to the clock input receiver and the first processing data receiver, the first multiplexor passing the clock signal output by the clock receiver when a first mux signal is in a first logic state, and passing the first signal output by the first processing data receiver when the first mux signal is in a second logic state; and

a second multiplexor connected to the first multiplexor and the first communication data driver, the second multiplexor passing a signal output from the first multiplexor when a second mux signal is in a first logic state, and passing an output data signal when the second mux signal is in a second logic state, the signal output from the first multiplexor being the clock signal when the first mux signal is in the first logic state, and being the first signal when the first mux signal is in the second logic state.

12. The circuit of claim 11 wherein the slave circuit further comprises a serial-to-parallel shift register connected to the internal circuit, the clock receiver, and the first processing data receiver, the clock signal output by the clock receiver clocking the shift register.

13. The circuit of claim 12 wherein the slave circuit further comprises a parallel-to-serial shift register connected to the internal circuit, the second multiplexor, and the clock receiver, the parallel-to-serial shift register outputting a data output signal in response to a parallel data signal from the internal circuit, the clock signal output by the clock receiver clocking the parallel-to-serial shift register.

14. The circuit of claim 13 wherein the slave circuit further includes a logic circuit connected to the first mux, the second mux, and the parallel-to-serial shift register, the logic circuit receiving the clock signal from the parallel-to-serial shift register, and setting the logic states of the first and second mux signals in response to commands extracted from the clock signal.

15. A physical layer device connectable to a transmission medium, the device comprising:

a media driver connectable to the transmission medium;

a media receiver connectable to the transmission medium;

a serializer/deserializer (serdes) connected to the media driver and the media receiver, the serdes outputting a master clock signal, an equivalent in-phase slave clock signal when in a calibration mode, and a data signal when in a data mode, the data signal representing a data signal received from the media receiver; and

a master circuit, the master circuit having;

a clock driver connected to output the master clock signal as a millivolt differential signal;

a first physical layer data driver connectable to output the slave clock signal as a millivolt differential signal when the serdes is in the calibration mode, and the data signal as a millivolt differential signal when the serdes is in the data mode.

16. The device of claim 15 wherein the master circuit further includes:

a first physical layer data receiver that receives a signal which represents the master clock signal during a first phase of the calibration mode, and represents the slave clock signal during a second phase of the calibration mode; and

an aligner connected to the first physical layer data receiver, the aligner receiving the master clock signal when the first physical layer data receiver receives the master clock signal, and the slave clock signal when the first physical layer data receiver receives the slave clock signal, the aligner having phase comparison circuitry that compares a phase of the master clock signal received by the aligner with a phase of the slave clock signal received by the aligner to determine a phase difference.

17. The device of claim 16 wherein the master circuit further comprises a phase delay circuit connected to the aligner, the serdes, and the first physical layer data driver, the aligner passing a plurality of signals to the phase delay circuit that indicates the phase difference, the phase delay circuit delaying the slave clock signal output from the serdes an amount so that the slave clock signal received by the aligner is substantially in phase with the master clock signal received by the aligner when in the calibration mode, the data signal being delayed the amount when in the data mode.

18. A method for operating a communication device having a physical layer device connected to a transmission medium and a processing device connected to the physical layer device, the method comprising the steps of:

outputting a master clock signal from the physical layer device over a first path;

receiving the master clock signal in the processing device from the first path;

outputting the master clock signal as a feedback master clock signal from the processing device over a feedback path;

receiving the feedback master clock signal in the physical layer device from the feedback path;

determining a phase of the feedback master clock signal;

outputting a slave clock signal from the physical layer device over a second path after the phase of the feedback master clock signal has been determined, the master clock signal and the slave clock signal having an equivalent frequency;

receiving the slave clock signal in the processing device from the second path;

outputting the slave clock signal as a feedback slave clock signal from the processing device over the feedback path;

receiving the feedback slave clock signal in the physical layer device from the feedback path;

determining a phase of the feedback slave clock signal;

comparing the phase of the feedback master clock signal with the phase of the feedback slave clock signal to determine a phase difference; and

adjusting a delay so that the phase of the feedback slave clock signal is substantially aligned with the phase of the feedback master clock signal.

19. The method of claim 18 and further comprising the steps of:

outputting a data clock signal from the physical layer device over the first path after the phase difference has been determined;

outputting an input data signal from the physical layer device over the second path after the phase difference has been determined, the input data signal and the data clock signal having an equivalent frequency; and

converting the input data signal to a parallel word by clocking the input data signal with the data clock signal.

20. A communication device comprising:

a physical layer device connectable to a transmission medium, the device having a master circuit, the master circuit having;

a clock output;

a first data output;

a first data input;

a phase comparator connected to the first data input; and

a processing circuit having a slave circuit, the slave circuit having;

a clock input connected to the clock output;

a second data input connected to the first data input;

a second data output connected to the first data input; and

a switch for connecting an output signal from the clock input to the second data output, or an output signal from the second data input to the second data output, the phase comparator comparing a phase of the output signal from the clock input with a phase of the output signal from the second data input to determine a phase difference.

21. A communication device for communication over a transmission medium, the communication device comprising:

a processing circuit comprising a first differential receiver, a second differential receiver, and a differential driver; and

a physical layer device connectable to the transmission medium such that data passes from the transmission medium through the physical layer device and to the processing circuit, the physical layer device comprising a first differential driver, a second differential driver, a differential receiver, and alignment circuitry, the alignment circuitry changing a second signal path such that a phase of a second signal received by the alignment circuitry from the second signal path substantially matches a phase of a first signal received by the alignment circuitry from a first signal path, the first signal path extending through the first differential driver of the physical layer device to the first differential receiver of the processing circuit and through the first differential receiver of the processing circuit to the differential driver of the processing circuit and through the differential driver of the processing circuit to the differential receiver of the physical layer device, the second signal path extending through the second differential driver of the physical layer device to the second differential receiver of the processing circuit and through the second differential receiver of the processing circuit to the differential driver of the processing circuit and through the differential driver of the processing circuit to the differential receiver of the physical layer device.

22. The communication device of claim 21, wherein a signal passes through the second signal path and has a propagation delay, the alignment circuitry changing the second signal path such that the propagation delay is changed.

23. The communication device of claim 21, wherein the first signal is received by the alignment circuitry at a first time, and the second signal is received by the alignment circuitry at a second time.

24. The communication device of claim 21, wherein the alignment circuitry comprises:

delay logic that receives a signal and outputs the signal to the second differential driver of the physical layer device, the delay logic having a plurality of delay select input leads; and

an aligner having a signal input lead and a plurality of delay select output leads, the delay select output leads being coupled to the delay select input leads of the delay logic, the signal input lead of the aligner being coupled to the differential receiver of the physical layer device.

25. The communication device of claim 21, wherein the data passes through the transmission medium and to the physical layer device at a rate of at least 1.25 gigabits per second, the transmission medium being a fiber optic cable.

26. The communication device of claim 21, wherein the physical layer device is a first integrated circuit, and wherein the processing circuit is a second integrated circuit.

27. The communication device of claim 21, wherein the processing circuit comprises multiplexer circuitry that selectively couples an output lead of the first differential receiver of the processing circuit or an output lead of the second differential receiver of the processing circuit to an input lead of the differential driver of the processing circuit.

28. The communication device of claim 27, wherein the physical layer device transmits a first command to the processing circuit in a calibration mode, the first command being transmitted as a differential signal, the first command causing the multiplexer circuitry to couple the output lead of the first differential receiver of the processing circuit to the input lead of the differential driver of the processing circuit,

and wherein the physical layer device transmits a second command to the processing circuit in the calibration mode, the second command being transmitted as a differential signal, the second command causing the multiplexer circuitry to couple the output lead of the second differential receiver of the processing circuit to the input lead of the differential driver of the processing circuit.

29. The communication device of claim 28, wherein the first and second commands are communicated from the first differential driver of the physical layer device to the first differential receiver of the processing circuit.

30. The communication device of claim 24, wherein the physical layer device further comprises:

a phase-locked-loop circuit that outputs a base clock signal and a series of phase-delayed signals, the phase-delayed signals being supplied to the aligner; and

a multiplier/switch circuit that frequency multiplies the base clock signal to generate the second signal, the multiplier/switch circuit selectively outputting the data or the second signal to the delay logic, the multiplier/switch circuit also frequency multiplying the base clock signal to generate the first signal, the multiplier/switch circuit outputting the first signal to the first differential driver of the physical layer device.

31. The communication device of claim 21, wherein the physical layer device is a first integrated circuit, wherein the processing circuit is a second integrated circuit, and wherein the processing circuit includes no clock recovery circuit that recovers any clock for the data.

32. An apparatus comprising:

a processing circuit integrated circuit (PCIC); and

a physical layer device integrated circuit (PLDIC) connectable to a fiber optic transmission medium such that data passes from the fiber optic transmission medium through the PLDIC and to the PCIC at a rate of at least 1.25 gigabits per second, a first differential signal path extending via a first pair of wires from the PLDIC to the PCIC, a second differential signal path extending via a second pair of wires from the PLDIC to the PCIC, a third differential signal path extending via a third pair of wires from the PCIC to the PLDIC, wherein the PLDIC comprises;

means for changing the second signal path such that a phase of a first signal received at the means substantially matches a phase of a second signal received at the means, the first signal passing from the PLDIC via the first differential signal path to the PCIC and then passing from the PCIC via the third signal path to the PLDIC, the second signal passing from the PLDIC via the second differential signal path to the PCIC and then passing from the PCIC via the third signal path to the PLDIC.

33. The apparatus of claim 32, wherein the data passes over one of the first and second pairs of wires, wherein a clock for the data passes over the other of the first and second pairs of wires, and wherein the PCIC comprises no clock recovery-circuit that recovers any clock for the data.

34. The apparatus of claim 32, wherein the means is also for transmitting a first command to the PCIC such that the PCIC causes the first signal to pass across the third pair of wires back to the PCIC, and wherein the means is also for transmitting a second command to the PCIC such that the PCIC causes the second signal to pass across the third pair of wires back to the PCIC.

35. An integrated circuit comprising:

a data receiver;

phase alignment circuitry coupled to the data receiver to identify a first clock signal having a phase aligned with a first signal received via the data receiver during a first time interval and to identify a second clock signal having a phase aligned with a second signal received via the data receiver during a second time interval;

a signal output driver; and

delay circuitry coupled to the signal output driver and the phase alignment circuitry to delay outputting a signal to the signal output driver according to a difference in phase between the first clock signal and the second clock signal.

36. A system comprising:

a first integrated circuit having a clock input, a first data input, a first data output and a calibration path selectively configurable to couple either the clock input to the first data output or the first data input to the first data output; and

a second integrated circuit having a clock output coupled to the clock input, a second data output coupled to the first data input, a second data input coupled to the first data output and phase detection circuitry coupled to the second data input to detect the phase of a periodic signal output to the first integrated circuit by either the second data output or the clock output and propagated to the phase detection circuitry via the calibration path, the first data output and the second data input.

37. The system of claim 36, wherein the first integrated circuit receives a command from the second integrated circuit via the clock input, wherein if the command is a first command then the calibration path is configured such that the clock input is coupled to the first data output, and wherein if the command is a second command then the calibration path is configured such that the first data input is coupled to the first data output.

38. The system of claim 36, wherein the phase detection circuitry detects a phase of a first periodic signal at a first time, the first periodic signal being output to the first integrated circuit by the clock output and being propagated to the phase detection circuitry via the calibration path, the first data output and the second data input, and wherein the phase detection circuitry detects a phase of a second periodic signal at a second time, the second periodic signal being output to the first integrated circuit by the second data output and being propagated to the phase detection circuitry via the calibration path, the first data output and the second data input.

39. The system of claim 38, wherein the second integrated circuit further comprises delay circuitry, the delay circuitry changing a propagation delay on the second integrated circuit such that the phase of the second periodic signal received at the phase detection circuitry substantially matches the phase of the first periodic signal received at the phase detection circuitry.

40. A system comprising:

a first integrated circuit including a first data output driver, a first data receiver, a clock receiver, and a calibration path having selectable first and second configurations, the calibration path coupling the clock receiver to the first data output driver when in the first configuration and coupling the first data receiver to the first data output driver when in the second configuration; and

a second integrated circuit including a second data receiver coupled to the first data output driver, a second data output driver coupled to the first data receiver, a clock output driver coupled to the clock receiver, and phase detection circuitry coupled to the second data receiver to detect the phase of a first periodic signal output by the clock output driver and propagated to the phase detection circuitry via the calibration path when the calibration path is in the first configuration and to detect the phase of a second periodic output by the second data output driver and propagated to the phase detection circuitry via the calibration path when the calibration path is in the second configuration.

41. A method, comprising the steps of:

(a) transmitting a first periodic signal from a physical layer device integrated circuit (PLDIC) to a processing circuit integrated circuit (PCIC) via a first signal path, the first periodic signal then passing from the PCIC and to a phase detector on the PLDIC via a third signal path;

(b) detecting on the phase detector of the PLDIC a phase of the first periodic signal;

(c) after step (b), transmitting a second periodic signal from the PLDIC to the PCIC via a second signal path, the second periodic signal then passing from the PLDIC and to the phase detector on the PLDIC via the third signal path;

(d) detecting on the phase detector of the PLDIC a phase of the second periodic signal;

(e) modifying a signal path on the PCIC such that the phase of the second periodic signal detected in (d) substantially matches the phase of the first periodic signal detected in (b); and

(f) receiving data onto the PLDIC serially from a transmission medium at a rate of at least 1.25 gigabits per second, the data and a clock for the data being transmitted from the PLDIC to the PCIC via the first signal path and the second signal path such that the data passes serially from the PLDIC to the PCIC at a rate of at least 1.25 gigabits per second.

42. The method of claim 41, wherein the transmission medium is a fiber optic cable.

43. The method of claim 41, wherein the PCIC comprises no clock recovery circuit that recovers a clock signal from the data that passes serially from the PLDIC to the PCIC.

44. A method, comprising the steps of:

(a) transmitting from an integrated circuit a first signal, the first signal being transmitted from the integrated circuit via a first driver;

(b) receiving onto the integrated circuit the first signal, the first signal being received onto the integrated circuit via a receiver;

(c) transmitting from the integrated circuit a second signal, the second signal being transmitted from the integrated circuit via a second driver;

(d) receiving onto the integrated circuit the second signal, the second signal being received onto the integrated circuit via the receiver;

(e) changing a path on the integrated circuit through which the second signal passes such that the second signal received onto the integrated circuit is synchronized with respect to the first signal received onto the integrated circuit; and

(f) receiving data onto the integrated circuit serially from a transmission medium at a rate of at least 1.25 gigabits per second, the data and a clock for the data being transmitted from integrated circuit via the first driver and the second driver such that the data passes serially from the integrated circuit at a rate of at least 1.25 gigabits per second.

45. The method of claim 44, further comprising the step of:

after (b) and before (c), transmitting from the integrated circuit an embedded command, the embedded command being transmitted from the integrated circuit via a driver.

46. The method of claim 45, wherein the driver from which the embedded command is transmitted from the integrated circuit is the first driver.

47. The method of claim 44, wherein the first driver is a differential driver, wherein the second driver is a differential driver, wherein the receiver is a differential receiver, and wherein the transmission medium is a fiber optic cable.