Equalization and decision-directed loops with trellis demodulation in high definition TV

• US 6,775,334 B1
• Filed: 11/03/1999
• Issued: 08/10/2004
• Est. Priority Date: 11/03/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Tan, Loke Kun, Jaffe, Steven T., Liu, Tian-Min
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): MUNOZ, GUILLERMO
• Application Number:
  US09/433,733
• Time in Patent Office: 1,742 Days
• Field of Search: 375/341, 375/340, 375/233, 375/234, 375/348, 375/230, 375/232
• US Class Current: 375/341
• CPC Class Codes: H04B 1/68 for wholly or partially suppressing the carrier or one side band
• CPC Class Codes: H04L 2025/03382 Single of vestigal sideband
• CPC Class Codes: H04L 2025/0342 QAM
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 2025/03503 as a combination of feedback and prediction filters
• CPC Class Codes: H04L 2027/0032 at baseband and passband
• CPC Class Codes: H04L 2027/0042 the equaliser providing the offset correction per se
• CPC Class Codes: H04L 2027/0057 quadrature phase
• CPC Class Codes: H04L 2027/0067 Phase error detectors
• CPC Class Codes: H04L 2027/0087 Out-of-band signals, (e.g. pilots)
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 27/02 Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation H04L27/32 takes precedence
• CPC Class Codes: H04L 27/066 Carrier recovery circuits H04L27/2271 takes precedence
• CPC Class Codes: H04L 27/2273 associated with quadrature demodulation, e.g. Costas loop
• CPC Class Codes: H04L 27/3427 in which the constellation is the n - fold Cartesian product of a single underlying two-dimensional constellation
• CPC Class Codes: H04L 27/3827 in which the carrier is recovered using only the demodulated baseband signals
• CPC Class Codes: H04N 11/24 High-definition television systems
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo
• CPC Class Codes: H04N 5/211 Ghost signal cancellation H04N23/81 takes precedence
• CPC Class Codes: H04N 5/44 : Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27

Abstract

Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE'"'"'s ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

Claims

1. In a digital receiver,

a feedforward equalizer (FFE) adapted to process a digital input signal, the FFE having a plurality of adjustable taps that control its frequency response;

a trellis decoder adapted to produce tentative evaluations of the processed input signal and an FFE error signal;

a decision feedback equalizer (DFE) adapted to process the tentative evaluations;

means for coupling the trellis decoder to the DFE to process the tentative evaluations;

means for coupling a combination of the outputs from the FFE and the DFE to the trellis decoder; and

means responsive to the FFE error signal from the trellis decoder for adjusting the taps of the FFE to reduce the error.

2. The digital receiver of claim 1, in which the DFE has a plurality of adjustable taps that control its frequency response, the digital receiver additionally comprising means responsive to the FFE error signal for adjusting the taps of the DFE to reduce the error.

3. The digital receiver of claim 2, additionally comprising a timing loop that generates a timing reference and means responsive to the FFE error signal for adjusting the timing reference.

4. The digital receiver of claim 3, additionally comprising a carrier loop that generates a derotating signal for the digital input signal and means responsive to the FFE error signal for adjusting the derotating signal.

5. The digital receiver of claim 1, additionally comprising a timing loop that generates a timing reference and means responsive to the FFE error signal for adjusting the timing reference.

6. The digital receiver of claim 1, additionally comprising a carrier loop that generates a derotating signal and means responsive to the FFE error signal for adjusting the derotating signal.

7. The digital receiver of claim 1, in which the trellis decoder generates a timing reference error signal representing less delay than the FFE error signal.

8. The digital receiver of claim 1, in which the trellis decoder generates a timing reference error signal and a derotating error signal representing less delay than the timing reference error signal, the receiver additionally comprising means responsive to the derotating error signal for adjusting the derotating signal and means responsive to the timing reference error signal for adjusting the timing reference.

9. The digital receiver of claim 8, in which the trellis decoder generates a timing reference error signal representing less delay than the FFE error signal.