Circuit design for high-speed digital communication

• US 6,775,339 B1
• Filed: 08/27/1999
• Issued: 08/10/2004
• Est. Priority Date: 08/27/1999
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Birrittella, Mark S., Wildes, Paul T.
• Primary Examiner(s): Bayard, Emmanuel
• Assistant Examiner(s): Nguyen, Dung X.
• Application Number:
  US09/384,906
• Time in Patent Office: 1,810 Days
• Field of Search: 375/354, 375/377, 375/359, 375/362, 375/219, 375/220, 375/244, 375/259, 375/355, 375/356, 370/350, 370/503, 713/400, 713/401, 713/503, 711/5, 711/163, 327/141, 327/144, 327/145
• US Class Current: 375/354
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

The present invention provides a system for efficient, high speed, high bandwidth, digital communication where transmit distances are greater than a single clock period. The digital system operates based on a system clock. Within the digital system a transmit module transmits data along with a capture clock signal to a receive module where the transmission time between the modules is greater than one period of the system clock. The capture clock operates in a known relationship to the system clock at a frequency at least twice as slow as the system clock. The digital system also has a synchronizing clock that operates at the same frequency as the forwarded clock. When the data arrives at the receive module it is captured by a pair of memory devices operating on different phases of the capture clock. The memory devices feed the data to a multiplexor that selects, as a function of the synchronizing clock, between the outputs of the two memory devices. At this point the data has been synchronized with the system clock and can be captured using the system clock for processing in the receive module.

Claims

1. A system for synchronous communication comprising:

a system clock;

a capture clock having a first and second phase, wherein the capture clock operates at a frequency at least two times slower than the system clock;

a synchronizing clock, wherein the synchronizing clock operates at the same frequency as the capture clock; and

a first and a second module, wherein the first module comprises;

one or more data output nodes for transmitting data; and

a clock output node for transmitting the capture clock signal;

and wherein the second module comprises;

a plurality of data input nodes for receiving data transmitted by the data output nodes of the first module;

a capture clock input node for receiving the capture clock from the clock output node of the first module; and

a receive circuit for synchronizing the data with the system clock,

wherein the receive circuit comprises;

a first memory device connected to a first data input node and operating on the first phase of the capture clock;

a second memory device connected to the first data input node and operating on the second phase of the capture clock; and

a multiplexor connected to the first and second memory devices, wherein the multiplexor selects between the first and second memory devices as a function of the synchronizing clock.

2. The system of claim 1, wherein the synchronizing clock is delayed with respect to the system clock.

3. The system of claim 2, wherein the delay is less than one period of the system clock.

4. The system of claim 1, wherein the first memory devices are selected from the group consisting of positive triggered D latches and positive edge triggered D flip-flops;

and

wherein the second memory devices are selected from the group consisting of negative triggered D latches and negative edge triggered D flip-flops.

5. The system of claim 1, wherein the distance between the first and second modules is such that it takes greater than one period of the system clock for information to travel from the first module to the second module.

6. The system of claim 1, wherein the synchronizing clock and system clock are generated external to the first and second modules.

7. The system of claim 1, wherein the synchronizing clock is generated in the first and second modules.

8. The system of claim 1, wherein the first module further comprises:

an internal system clock having a frequency different from the system clock; and

wherein the second module further comprises;

an internal system clock having a frequency equal to the internal system clock of the first module.

9. The system of claim 8, wherein the internal system clocks of both the first and second modules operate at a frequency double that of the system clock.

10. An integrated circuit for synchronous communication comprising:

a system clock;

a capture clock having a first and second phase, wherein the capture clock operates at a frequency at least two times slower than the system clock;

a synchronizing clock, wherein the synchronizing clock operates at the same frequency as the capture clock;

a transmit subcircuit comprising;

at least one transmit memory device, each transmit memory device having an output node; and

a clock output for transmitting the capture clock;

a receive subcircuit comprising;

at least one first memory device, each first memory device having a data input node, a data output node and a clock input node, each data input node connected to a corresponding output node of the transmit circuit and the clock input node connected to the capture clock, wherein each first memory device operates on the first phase of the capture clock;

at least one second memory device, each second memory device having a data input node, a data output node and a clock input node, each data input node connected to an output node of the transmit circuit and the clock input node connected to the capture clock, wherein each second memory device operates on the second phase of the capture clock;

at least one multiplexor, each multiplexor having a first input node, a second input node, an output select node, and an output node, each first input node connected to a data output node of one of the at least one first memory devices, each second input node connected to a data output node of one of the at least one second memory devices and each output select node connected to the synchronizing clock; and

at least one input memory device, each input memory device having an input node connected to the output node of one of the at least one multiplexors, a clock input node connected to the system clock and an output node.

11. The integrate circuit of claim 10, wherein the synchronizing clock is delayed with respect to the system clock.

12. The integrated circuit of claim 11, wherein the delay is less than one period of the system clock.

13. The integrated circuit of claim 10, wherein the at least one first memory device and the at least one input memory device are selected from the group consisting of positive triggered D latches and positive edge triggered D flip-flops, and the at least one second memory device is selected from the group consisting of negative triggered D latches and negative edge triggered D flip-flops.

14. The integrated circuit of claim 10, wherein the distance between the transmit subcircuit and receive subcircuit is such that it takes greater than one period of the system clock for information to travel from the transmit subcircuit to the receive subcircuit.

15. In a system operating at a first clock frequency a method of high speed synchronous communication comprising:

providing a receive module having a first and second memory device;

generating a forwarded clock, wherein the forwarded clock operates at a frequency at least half the first clock frequency and has first and second phases;

generating a receive clock at a frequency equal to the forwarded clock frequency;

transmitting data and the forwarded clock from a transmit module;

storing the data into the receive module, wherein storing includes storing data into the first memory device on the first phase of the forwarded clock and into the second memory device on the second phase of the forwarded clock;

synchronizing the data into the receive module using the receive clock; and

capturing the data in the receive module for further processing using the first clock.

16. The method of claim 15, wherein the receive clock is delayed with respect to the first clock.

17. The method of claim 16, wherein the delay is less than one period of the first clock.

18. The method of claim 15, wherein the first memory device is selected from the group consisting of positive triggered D latches and positive edge triggered D flip-flops, and the second memory device is selected from the group consisting of negative triggered D latches and negative edge triggered D flip-flops.

19. The method of claim 15, wherein the time from transmitting the data to storing the data takes greater than one period of the first clock.