Test method and apparatus for source synchronous signals
First Claim
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1. In a test system, a method for obtaining output signals from a device under test (“
- DUT”
) outputting source synchronous signals comprising the acts of;
(a) delaying a source synchronous output data signal from the DUT;
(b) delaying a source synchronous output clock signal from the DUT;
(c) holding the delayed source synchronous output data signal;
(d) releasing the delayed source synchronous output data signal as a function of the delayed source synchronous output clock signal; and
(e) comparing the released delayed source synchronous data signal with an expected value.
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Abstract
A method and associated apparatus for testing devices outputting source synchronous signals using automated test equipment (“ATE”). An output data signal and an output clock signal from such a source synchronous device under test are delayed using a delay network. The delay provides the time required to deskew path errors and to buffer and distribute the output clock signal. The output data signal appears relatively stable to the ATE by reading the output data signal using the output clock signal.
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Citations
26 Claims
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1. In a test system, a method for obtaining output signals from a device under test (“
- DUT”
) outputting source synchronous signals comprising the acts of;(a) delaying a source synchronous output data signal from the DUT;
(b) delaying a source synchronous output clock signal from the DUT;
(c) holding the delayed source synchronous output data signal;
(d) releasing the delayed source synchronous output data signal as a function of the delayed source synchronous output clock signal; and
(e) comparing the released delayed source synchronous data signal with an expected value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
- DUT”
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16. An apparatus for testing an electronic device under test (“
- DUT”
) outputting source synchronous signals, the DUT including a data output terminal and a clock output terminal, the apparatus comprising;at least one comparator having a first input terminal adapted for coupling with a reference voltage and a second input terminal adapted for coupling with the data output terminal of the DUT, the comparator having an output terminal;
at least one first delay element coupled with the output terminal of the comparator, the at least one first delay element having a delayed output;
at least one second delay element adapted for coupling with the clock output terminal of the DUT, the at least one second delay element having a second delayed output;
a buffer having a first input terminal coupled with the delayed output from the at least one first delay element, the buffer having a second input terminal coupled with the second delayed output from the at least one second delay element;
a comparator coupled with the buffer, the comparator further coupled with an expected value signal; and
whereby the buffer is adapted to release a delayed source synchronous signal from the DUT upon receipt of a delayed clock signal from the DUT. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
- DUT”
Specification