Test method and apparatus for source synchronous signals

• US 6,775,637 B2
• Filed: 05/15/2003
• Issued: 08/10/2004
• Est. Priority Date: 10/01/1999
• Status: Expired due to Fees

• Current Assignee: Credence Systems Corporation (COHU Incorporated)
• Original Assignee: NPTest, LLC
• Inventors: Garcia, Rodolfo F.
• Primary Examiner(s): SHAH, KAMINI S
• Application Number:
  US10/439,819
• Publication Number:
  US 20030229466A1
• Time in Patent Office: 453 Days
• Field of Search: 702/117, 702/79, 714/733, 714/734, 714/731, 714/744, 713/401, 348/512, 324/73.1
• US Class Current: 702/117
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24

Abstract

A method and associated apparatus for testing devices outputting source synchronous signals using automated test equipment (“ATE”). An output data signal and an output clock signal from such a source synchronous device under test are delayed using a delay network. The delay provides the time required to deskew path errors and to buffer and distribute the output clock signal. The output data signal appears relatively stable to the ATE by reading the output data signal using the output clock signal.

Claims

1. In a test system, a method for obtaining output signals from a device under test (“

DUT”

) outputting source synchronous signals comprising the acts of;

(a) delaying a source synchronous output data signal from the DUT;

(b) delaying a source synchronous output clock signal from the DUT;

(c) holding the delayed source synchronous output data signal;

(d) releasing the delayed source synchronous output data signal as a function of the delayed source synchronous output clock signal; and

(e) comparing the released delayed source synchronous data signal with an expected value.

2. The method of claim 1 wherein the operation of holding comprises latching the delayed source synchronous output data signal.

3. The method of claim 2 wherein the operation of releasing comprises strobing the latched delayed source synchronous output data signal as a function of the delayed source synchronous output clock signal.

4. The method of claim 1 wherein the operation of delaying the source synchronous output data signal further comprises deskewing path errors of the source synchronous output data signal.

5. The method of claim 1 wherein the operation of delaying the source synchronous output clock signal further comprises deskewing path errors of the source synchronous output clock signal.

6. The method of claim 1 further comprising, prior to the operation of delaying a source synchronous output data signal from the DUT, comparing the source synchronous output data signal to a reference voltage.

7. The method of claim 6 further comprising comparing the source synchronous output data signal to a high reference voltage.

8. The method of claim 6 further comprising comparing the source synchronous output data signal to a low reference voltage.

9. The method of claim 6 further comprising edge glitching the compared source synchronous output data signal.

10. The method of claim 6 further comprising positive edge glitching the compared source synchronous output data signal.

11. The method of claim 6 further comprising negative edge glitching the compared source synchronous output data signal.

12. The method of claim 6 further comprising triggering a ramp signal as a function of the delayed source synchronous output data signal.

13. The method of claim 12 further comprising comparing the ramp signal to at least one reference voltage.

14. The method of claim 13 further comprising gating the delayed source synchronous output data signal with the delayed source synchronous output clock signal.

15. The method of claim 14 wherein the operation of releasing comprises triggering a flip-flop output as a function of the delayed source synchronous output data signal.

16. An apparatus for testing an electronic device under test (“

DUT”

) outputting source synchronous signals, the DUT including a data output terminal and a clock output terminal, the apparatus comprising;

at least one comparator having a first input terminal adapted for coupling with a reference voltage and a second input terminal adapted for coupling with the data output terminal of the DUT, the comparator having an output terminal;

at least one first delay element coupled with the output terminal of the comparator, the at least one first delay element having a delayed output;

at least one second delay element adapted for coupling with the clock output terminal of the DUT, the at least one second delay element having a second delayed output;

a buffer having a first input terminal coupled with the delayed output from the at least one first delay element, the buffer having a second input terminal coupled with the second delayed output from the at least one second delay element;

a comparator coupled with the buffer, the comparator further coupled with an expected value signal; and

whereby the buffer is adapted to release a delayed source synchronous signal from the DUT upon receipt of a delayed clock signal from the DUT.

17. The apparatus of claim 16 wherein the buffer comprises a latch.

18. The apparatus of claim 16 wherein the buffer comprises an AND gate.

19. The apparatus of claim 16 further comprising an edge glitcher coupled between the at least one comparator and the at least one first delay element.

20. The apparatus of claim 16 wherein the at least one first delay element comprises a programmable delay element.

21. The apparatus of claim 20 further comprising a flip flop coupled with the programmable delay element, the at least one first delay element, and the buffer.

22. The apparatus of claim 20 wherein the at least one second delay element comprises a programmable delay element.

23. The apparatus of claim 20 further comprising a ramp generator coupled with the at least one first delay element.

24. The apparatus of claim 23 further comprising at least one second comparator coupled with the ramp generator.

25. The apparatus of claim 24 further comprising an AND gate coupled with the at least one second comparator and the at least one second delay element.

26. The apparatus of claim 25 further comprising a flip flop operably coupled with the AND gate.