Digital matched filter

• US 6,775,684 B1
• Filed: 06/02/2000
• Issued: 08/10/2004
• Est. Priority Date: 06/03/1999
• Status: Expired due to Fees

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Sato, Yuichi, Toyoyama, Shinji
• Primary Examiner(s): Chaki, Kakali
• Assistant Examiner(s): Do, Chat C.
• Application Number:
  US09/586,596
• Time in Patent Office: 1,530 Days
• Field of Search: 708/300-323, 370/206, 370/441, 375/308, 375/232, 375/295, 375/152
• US Class Current: 708/314
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: H04B 1/7093 Matched filter type

Abstract

A digital matched filter has a serial-to-parallel conversion circuit that converts input data fed thereto in serial form into n sets of parallel data and a plurality of delay circuits that each output serial data fed thereto with a delay corresponding to n sets of data. The serial-to-parallel conversion circuit and the delay circuits are each fed with n clocks having different phases, and are composed of delay devices connected in n groups of serially connected delay devices so that the input data is shifted in synchronism with the rising edges of those n clocks. The outputs from the individual delay devices are multiplied by codes by multipliers, and the results of those multiplications are added together and output as output data by an adder.

Claims

1. A digital matched filter comprising:

a serial-to-parallel conversion circuit for converting serial data fed thereto into n sets of parallel data (where n is a natural number);

m-stage delay circuits (where m is a natural number) connected in series and provided as stages following the serial-to-parallel conversion circuit, the delay circuits each outputting the n sets of parallel data fed thereto with a delay corresponding to n sets of data; and

a correlation value calculation circuit for calculating a correlation value between n×

(m+1) sets of data output individually from the serial-to-parallel conversion circuit and from the m-stage delay circuits and n×

(m+1) bit back-diffusion codes,

wherein the serial-to-parallel conversion circuit and the m-stage delay circuits are each fed with n clocks having different phases.

2. A digital matched filter as claimed in claim 1,

wherein the correlation value calculation circuit comprises:

n×

(m+1) multipliers for multiplying on a one-set-of-data-by-one-bit-code basis the n×

(m+1) sets of data obtained as m+1 suits of n sets of parallel data output individually from the serial-to-parallel conversion circuit and from the m-stage delay circuits by the back-diffusion codes; and

an adder for adding together every set of n×

(m+1) sets of data output individually from the multipliers.

3. A digital matched filter as claimed in claim 1,

wherein the serial-to-parallel conversion circuit has n delay devices to which the serial data is fed, and

wherein the m-stage delay circuits each has n delay devices to which the n sets of parallel data is fed, one set to one delay device, from the serial-to-parallel conversion circuit or another of the delay circuits, whichever is provided as an immediately preceding stage.

4. A digital matched filter as claimed in claim 3,

wherein the delay devices provided in each of the m-stage delay circuits and the delay devices provided in the serial-to-parallel conversion circuit or another of the delay circuits, whichever is provided as an immediately preceding stage, are connected individually in series in one-to-one correspondence, and

wherein the serial-to-parallel conversion circuit and the m-stage delay circuits are each fed with n clocks having different phases in such a way that each of n delay device groups each composed of m+1 delay devices that are connected in series with one another receives a clock having an identical phase.

5. A digital matched filter as claimed in claim 4,

wherein the correlation value calculation circuit comprises:

n×

(m+1) multipliers for multiplying on a one-set-of-data-by-one-bit-code basis the n×

(m+1) sets of data obtained as m+1 suits of n sets of parallel data output individually from the serial-to-parallel conversion circuit and from each of the m-stage delay circuits; and

an adder for adding together every set of n×

(m+1) sets of data output individually from the multipliers.

6. A digital matched filter as claimed in claim 5,

wherein the back-diffusion codes fed to the multipliers are shifted cyclically by being shifted each time the serial data switches from one sequence to a next.

7. A digital matched filter as claimed in claim 6,

wherein, when the back-diffusion codes fed to the multipliers are shifted n times, the multipliers receive the original back-diffusion codes.

8. A digital matched filter comprising:

a first delay device group having m-stage delay devices (where m is a natural number) connected in series with one another and receiving input data, in serial form, at the first-stage delay device thereof;

n−

1 second delay device groups (where n is a natural number) each having m-stage delay devices connected in series with one another;

n−

1 select circuits for feeding either data output from the last-stage delay devices of the individual second delay device groups or input data to the first-stage delay devices of the same second delay device groups individually; and

a correlation value calculation circuit for calculating a correlation value between m×

n sets of data output individually from the delay devices and m×

n bit back-diffusion codes.

9. A digital matched filter as claimed in claim 8,

wherein the correlation value calculation circuit comprises:

m×

n multipliers for multiplying on a one-set-of-data-by-one-bit-code basis the m×

n sets of data output individually from the delay devices constituting the first and second delay device groups by the back-diffusion codes; and

an adder for adding together every set of m×

n sets of data output individually from the multipliers.

10. A digital matched filter as claimed in claim 9,

wherein the back-diffusion codes fed to the multipliers are shifted cyclically by being shifted each time the serial data switches from one sequence to a next.

11. A digital matched filter as claimed in claim 10,

wherein, when the back-diffusion codes fed to the multipliers are shifted n times, the multipliers receive the original back-diffusion codes.

12. A digital matched filter, comprising:

a first delay device group having m-stage delay devices (where m is a natural number) connected in series with one another and receiving input data, in serial form, at the first-stage delay device thereof;

n−

1 second delay device groups (where n is a natural number) each having m-stage delay devices connected in series with one another;

n−

1 select circuits for feeding either data output from the last-stage delay devices of the individual second delay device groups or input data to the first-stage delay devices of the same delay device groups individually; and

a correlation value calculation circuit for calculating a correlation value between m×

n sets of data output individually from the delay devices and m×

n bit back-diffusion codes,

wherein all of the delay devices provided in the first delay device group and the second-to-last-stage delay devices provided in the individual second delay device groups are fed with a clock having an identical phase, and

wherein the first-stage delay devices of the individual second delay device groups are fed with clocks having different phases.

13. A digital matched filter as claimed in claim 12,

wherein, when data is shifted simultaneously to all of the delay devices provided in the first delay device group and the second-to-last-stage delay devices provided in the individual second delay device groups, the select circuits select data latched in the last-stage delay devices provided in the individual second delay device groups and shifts that data to the first-stage delay devices provided in the individual second delay device groups.

14. A digital matched filter as claimed in claim 13,

wherein the correlation value calculation circuit comprises:

m×

n multipliers for multiplying on a one-set-of-data-by-one-bit-code basis the m×

n sets of data output individually from the delay devices constituting the first and second delay device groups by the back-diffusion codes; and

an adder for adding together every set of m×

n sets of data output individually from the multipliers.

15. A digital matched filter as claimed in claim 14,

wherein, when the serial data switches n times, the select circuits select the data output from the last-stage delay devices.

16. A digital matched filter as claimed in claim 15,

wherein, when the back-diffusion codes fed to the multipliers are shifted n times, the multipliers receive the original back-diffusion codes.

17. A digital matched filter as claimed in claim 12, wherein

the correlation value calculation circuit comprises:

m×

n multipliers for multiplying on a one-set-of-data-by-one-bit-code basis the m×

n sets of data output individually from the delay devices constituting the first and second delay device groups by the back-diffusion codes; and

an adder for adding together every set of m×

n sets of data output individually from the multipliers.

18. A digital matched filter, comprising:

a serial-to-parallel conversion circuit for converting serial data fed thereto into n sets of parallel data (where n is a natural number);

m-stage delay circuits (where m is a natural number) connected in series and provided as stages following the serial-to-parallel conversion circuit, the delay circuits each outputting the n sets of parallel data fed thereto with a delay corresponding to n sets of data; and

a correlation value calculation circuit for calculating a correlation value between n×

(m+1) sets of data output individually from the serial-to-parallel conversion circuit and from the m-stage delay circuits and n×

(m+1) bit back-diffusion codes, the correlation value calculation circuit comprising;

n×

(m+1) multipliers for multiplying on a one-set-of-data-by-one-bit-code basis the n×

(m+1) sets of data obtained as m+1 suits of n sets of parallel data output individually from the serial-to-parallel conversion circuit and from the m-stage delay circuits by the back-diffusion codes; and

an adder for adding together every set of n×

(m+1) sets of data output individually from the multipliers,

wherein the back-diffusion codes fed to the multipliers are shifted cyclically by being shifted each time the serial data switches from one sequence to a next.

19. A digital matched filter as claimed in claim 18,

wherein, when the back-diffusion codes fed to the multipliers are shifted n times, the multipliers receive the original back-diffusion codes.

20. A digital matched filter, comprising:

a first delay device group having m-stage delay devices (where m is a natural number) connected in series with one another and receiving input data, in serial form, at the first-stage delay device thereof;

n−

1 second delay device groups (where n is a natural number) each having m-stage delay devices connected in series with one another;

n−

1 select circuits for feeding either data output from the last-stage delay devices of the individual second delay device groups or input data to the first-stage delay devices of the same second delay device groups individually; and

a correlation value calculation circuit for calculating a correlation value between m×

n sets of data output individually from the delay devices and m×

n bit back-diffusion codes,

wherein, when the serial data switches n times, the select circuits select the data output from the last-stage delay devices.

21. A digital matched filter as claimed in claim 20,

wherein, when the select circuits select the data output from the last-stage delay devices, pulses are produced simultaneously in the clocks fed to the first-stage delay devices of the individual second delay device groups.

22. A digital matched filter as claim in claim 20, wherein

the correlation value calculation circuit comprises:

m×

n multipliers for multiplying on a one-set-of-data-by-one-bit-code basis the m×

n sets of data output individually from the delay devices constituting the first and second delay device groups by the back-diffusion codes; and

an adder for adding together every set of m×

n sets of data output individually from the multipliers.