Host-fabric adapter and method of connecting a host system to a channel-based switched fabric in a data network
First Claim
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1. A host-fabric adapter installed at a host system for connecting to a switched fabric of a data network, comprising:
- a host interface which reads and writes data from a host memory of the host system;
a serial interface which receives and transmits data from said switched fabric; and
a Micro-Engine (ME) operatively coupled to the host interface and operatively coupled to the serial interface, wherein said Micro-Engine (ME) issues a host request to said host interface for a host transaction including an address and length of host data to be fetched from said host memory, and an End-Of-Cell (EOC) indicator which indicates that a cell has been built for transmission via said serial interface, and which starts working on a different task without waiting for the corresponding host response of the host request from said host interface.
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Abstract
A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network. The host-fabric adapter comprises a host interface arranged to interface a host memory of the host system; a serial interface arranged to receive and transmit data from said switched fabric; a Micro-Engine (ME) arranged to work on multiple tasks based on a Virtual Interface (VI) to support data transfers via the switched fabric, and configured to issue a host request to said host interface for a host transaction including an address and length of host data to be fetched from the host memory, and an End-Of-Cell (EOC) indicator which indicates that a cell has been built for transmission via the serial interface, and to begin working on a different task without waiting for the corresponding host response of the host request from the host interface; a Scheduler arranged to supply a request and a request VI number to said Micro-Engine (ME) for work; and a Request Comparator arranged to check the current VI that is being worked on by the Micro-Engine (ME), and to generate an acknowledgment ACK or a negative acknowledgment NACK to the Scheduler depending upon whether the request VI number is currently being worked on by the Micro-Engine (ME).
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Citations
27 Claims
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1. A host-fabric adapter installed at a host system for connecting to a switched fabric of a data network, comprising:
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a host interface which reads and writes data from a host memory of the host system;
a serial interface which receives and transmits data from said switched fabric; and
a Micro-Engine (ME) operatively coupled to the host interface and operatively coupled to the serial interface, wherein said Micro-Engine (ME) issues a host request to said host interface for a host transaction including an address and length of host data to be fetched from said host memory, and an End-Of-Cell (EOC) indicator which indicates that a cell has been built for transmission via said serial interface, and which starts working on a different task without waiting for the corresponding host response of the host request from said host interface. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
an address translation interface provides an interface for address translation, and which is addressable by write data and system controls from said Micro-Engine (ME), via a system data bus and a system control bus;
a context memory interface which provides an interface to a context manager, and which is addressable by write data and system controls from said Micro-Engine (ME), via said system data bus and said system control bus, for providing the necessary context for a work queue pair (WQP) used for sending and receiving data packets;
a local bus interface which provides an interface to a local bus, and which is addressable by write data and system controls from said Micro-Engine (ME), via said system data bus and said system control bus, for supporting system accessible context connections and data transfer operations;
a completion queue/doorbell manager interface which provides an interface to completion queues, and doorbell and memory registration rules, and which is addressable by write data and system controls from said Micro-Engine (ME), via said system data bus and said system control bus; and
a first-in/first-out (FIFO) interface which provides an interface to said switched fabric via said serial interface, and which is addressable by write data and system controls from said Micro-Engine (ME), via said system data bus and said system control bus, for enabling exchange of requests and/or data packets from said switched fabric.
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7. The host-fabric adapter as claimed in claim 6, wherein said Micro-Engine (ME) comprises:
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one or more Data Multiplexers arranged to supply appropriate interface data based on an ME instruction;
an Instruction Memory arranged to provide said ME instruction based on downloadable microcode;
an Arithmetic Logic Unit (ALU) arranged to perform mathematical, logical and shifting operations, and supply write data to the host interface, the address translation interface, the VI context memory interface, the local bus interface, the completion queue/doorbell manager interface and the FIFO interface, via said system write data bus; and
an Instruction Decoder arranged to supply system controls to the host interface, the address translation interface, the context memory interface, the local bus interface, the completion queue/doorbell manager interface and the FIFO interface, via said system control bus, to execute said ME instruction from said Instruction Memory to control operations of said Data Multiplexers, and to determine functions of said Arithmetic Logic Unit (ALU).
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8. The host-fabric adapter as claimed in claim 7, wherein said ME instruction includes an OpCode field used to control said Arithmetic Logic Unit (ALU), and a destination field and a source field used to control operation of one or more Data Multiplexers.
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9. The host-fabric adapter as claimed in claim 7, wherein said one or more Data Multiplexers supply two parallel 32-bit buses (A-bus and B-bus) data inputs based on decode of the destination field and the source field of each ME instruction from the host interface, the address translation interface, the context memory interface, the local bus interface, the completion queue/doorbell manager interface, and the FIFO interface to said Arithmetic Logic Unit (ALU).
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10. The host-fabric adapter as claimed in claim 7, wherein said Arithmetic Logic Unit (ALU) performs functions that are based on the OpCode field of each ME instruction, including, but are not limited to, Add, Subtract, OR, XOR, AND, Compare, Rotate Right, Shift Left, Bit test and Move (pass through) operations, and said Instruction Decoder decodes said ME instruction and provides function select signals to said Arithmetic Logic Unit (ALU) to perform selected ME functions.
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11. The host-fabric adapter as claimed in claim 7, wherein said Instruction Memory corresponds to a static random-access-memory (SRAM) provided to store microcode that are downloadable for providing said ME instruction to said Instruction Decoder.
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12. The host-fabric adapter as claimed in claim 1, wherein said host interface, said serial interface and said Micro-Engine (ME) are configured in accordance with the “
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Virtual Interface (VI) Architecture Specification”
, the “
Next Generation Input/Output (NGIO) Specification” and
the “
InfiniBand™
Specification”
.
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Virtual Interface (VI) Architecture Specification”
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13. A host-fabric adapter installed at a host system for connecting to a switched fabric of a data network, comprising:
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a Micro-Engine (ME) arranged to work on multiple tasks based on a Virtual Interface (VI) to support data transfers via said switched fabric;
a Scheduler arranged to supply a request and a request VI number to said Micro-Engine (ME) for work; and
a Request Comparator operatively coupled to said Micro-Engine (ME) and operatively coupled to said Scheduler, said Request Comparator arranged to check the current VI that is being worked on by said Micro-Engine (ME), and to generate an acknowledgment ACK or a negative acknowledgment NACK to said Scheduler depending upon whether the request VI number is currently being worked on by said Micro-Engine (ME);
a host interface which provides an interface to said host system, and which is addressable by write data and system controls from said Micro-Engine (ME), via a system data bus and a system control bus;
a serial interface which receives and transmits data from said switched fabric;
an address translation interface provides an interface for address translation, and which is addressable by write data and system controls from said Micro-Engine (ME), via a system data bus and a system control bus;
a context memory which provides an interface to a context manager, and which is addressable by write data and system controls from said Micro-Engine (ME), via said system data bus and said system control bus, for providing the necessary context for a work queue pair (WQP) used for sending and receiving data packets;
a local bus interface which provides an interface to a local bus, and which is addressable by write data and system controls from said Micro-Engine (ME), via said system data bus and said system control bus, for supporting system accessible context connections and data transfer operations;
a completion queue/doorbell manager interface which provides an interface to completion queues, and doorbell and memory registration rules, and which is addressable by write data and system controls from said Micro-Engine (ME), via said system data bus and said system control bus; and
a first-in/first-out (FIFO) interface which provides an interface to said switched fabric via said serial interface, and which is addressable by write data and system controls from said Micro-Engine (ME), via said system data bus and said system control bus, for enabling exchange of requests and/or data packets from said switched fabric, wherein each of said host interface, said serial interface, said address translation interface, said context memory, said local bus interface, said completion queue/doorbell manager interface, and said first-in/first-out (FIFO) interface are operatively coupled to said Micro-Engine (ME). - View Dependent Claims (14, 15, 16, 17, 18, 19)
one or more Data Multiplexers arranged to supply appropriate interface data based on an ME instruction;
an Instruction Memory arranged to provide said ME instruction based on downloadable microcode;
an Arithmetic Logic Unit (ALU) arranged to perform mathematical, logical and shifting operations, and supply write data to the host interface, the address translation interface, the VI context memory interface, the local bus interface, the completion queue/doorbell manager interface and the FIFO interface, via said system write data bus; and
an Instruction Decoder arranged to supply system controls to the host interface, the address translation interface, the VI context memory interface, the local bus interface, the completion queue/doorbell manager interface and the FIFO interface, via said system control bus, to execute said ME instruction from said Instruction Memory to control operations of said Data Multiplexers, and to determine the functions of said Arithmetic Logic Unit (ALU).
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15. The host-fabric adapter as claimed in claim 14, wherein said ME instruction includes an OpCode field used to control said Arithmetic Logic Unit (ALU), and a destination field and a source field used to control operation of one or more Data Multiplexers.
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16. The host-fabric adapter as claimed in claim 14, wherein said one or more Data Multiplexers supply two parallel 32-bit buses (A-bus and B-bus) data inputs based on decode of the destination field and the source field of each ME instruction from the host interface, the address translation interface, the VI context memory interface, the local bus interface, the completion queue/doorbell manager interface, and the FIFO interface to said Arithmetic Logic Unit (ALU).
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17. The host-fabric adapter as claimed in claim 14, wherein said Arithmetic Logic Unit (ALU) performs functions that are based on the OpCode field of each ME instruction including, but are not limited to, Add, Subtract, OR, XOR, AND, Compare, Rotate Right, Shift Left, Bit test and Move (pass through) operations, and said Instruction Decoder decodes said ME instruction and provides function select signals to said Arithmetic Logic Unit (ALU) to perform selected ME functions.
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18. The host-fabric adapter as claimed in claim 14, wherein said Instruction Memory corresponds to a static random-access-memory (SRAM) provided to store microcode that are downloadable for providing said ME instruction to said Instruction Decoder.
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19. The host-fabric adapter as claimed in claim 13, wherein said host interface, said serial interface and said Micro-Engine (ME) are configured in accordance with the “
-
Virtual Interface (VI) Architecture Specification”
, the “
Next Generation Input/Output (NGIO) Specification” and
the “
InfiniBand™
Specification”
.
-
Virtual Interface (VI) Architecture Specification”
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20. A host-fabric adapter, comprising:
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a host interface arranged to interface a host memory of a host system;
a serial interface arranged to receive and transmit data from a switched fabric;
a Micro-Engine (ME) operatively coupled to the host interface and operatively coupled to the serial interface, wherein said Micro-Engine (ME) is arranged to work on multiple tasks based on a Virtual Interface (VI) to support data transfers via said switched fabric, and configured to issue a host request to said host interface for a host transaction including an address and length of host data to be fetched from said host memory, and an End-Of-Cell (EOC) indicator which indicates that a cell has been built for transmission via said serial interface, and to begin working on a different task without waiting for the corresponding host response of the previous host request from said host interface;
a Scheduler arranged to supply a request and a request VI number to said Micro-Engine (ME) for work; and
a Request Comparator operatively coupled to said Micro-Engine (ME) and operatively coupled to said Scheduler, said Request Comparator arranged to check the current VI that is being worked on by said Micro-Engine (ME), and to generate an acknowledgment ACK or a negative acknowledgment NACK to said Scheduler depending upon whether the request VI number is currently being worked on by said Micro-Engine (ME). - View Dependent Claims (21, 22, 23, 24, 25, 26, 27)
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Specification
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Current AssigneeIntel Corporation
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Original AssigneeIntel Corporation
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InventorsBurton, Tom E., Ni, Jie, Gasbarro, Dominic J., Leitner, Brian M., Reohr, Richard D. Jr.
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Primary Examiner(s)Dang, Khanh
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Application NumberUS09/671,703Time in Patent Office1,412 DaysField of Search710/4, 710/11, 710/33, 710/34, 710/35, 710/36, 710/40, 710/51, 710/263, 710/65, 370/392, 370/390, 370/418, 370/429, 370/395.43, 370/399, 370/463US Class Current710/33CPC Class CodesH04L 49/30 Peripheral units, e.g. inpu...H04L 49/3009 Header conversion, routing ...H04L 49/3036 Shared queuingH04L 49/358 Infiniband SwitchesH04L 49/602 Multilayer or multiprotocol...
