Method, system and computer product to produce a computer-generated integrated circuit design

• US 6,775,806 B2
• Filed: 06/10/2002
• Issued: 08/10/2004
• Est. Priority Date: 06/10/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Li, Mu-Jing
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US10/166,210
• Publication Number:
  US 20030229860A1
• Time in Patent Office: 792 Days
• Field of Search: 716/1-18
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

The present invention provides a method, a system and a computer product for designing an integrated circuit using control software and employing the control software to dynamically generate rules files in response to changes made to the design in order to verify adherence of the changes made to the integrated circuit design with design rules.

Claims

1. A method for designing an integrated circuit using a computer having a memory, said method comprising:

mapping said integrated circuit into locations of said memory as multiple production layers with said multiple production layers including a plurality of data objects;

identifying locations in one of said multiple production layers at which to vary data object characteristics;

varying said characteristics at said locations to form varied data objects;

storing information in said memory concerning said varied data objects as a construction layer;

generating a rules file, in response to varying said characteristics, with said rules file including a sequence of commands to determine whether said varied data objects satisfy design rules, with the commands associated with said sequence being dependent upon the production layer, among said multiple production layers with which said varied objects are associated and the characteristics that are varied; and

distinguishing said varied data objects that violate said design rules from data objects satisfying said design rules.

2. The method as recited in claim 1 wherein said operations associated with said sequence are instructions included in CADENCE®

DESIGN FRAMEWORK II®

.

3. The method as recited in claim 1 wherein identifying locations in one of said multiple layers further includes identifying among said plurality of data objects, data objects having characteristics that violate said design rules, defining failed data objects, and storing data concerning said failed data objects at memory addresses in said memory associated with a marker layer, with said data including addresses in said memory of said failed data objects.

4. The method as recited in claim 1 wherein distinguishing said varied data objects further includes identifying said varied data objects having characteristics that satisfy said design rules, defining acceptable data objects, and staring data concerning said acceptable data objects at addresses in said memory associated with said one of said multiple production layers.

5. The method as recited in claim 1 wherein varying said characteristics further includes placing a data object at said locations.

6. The method as recited in claim 1 wherein varying said characteristics further includes removing a data object at said locations.

7. The method as recited in claim 1 wherein varying said characteristics further includes modifying a data object at said locations.

8. The method as recited in claim 1 wherein distinguishing said varied data objects further includes storing data concerning said varied data objects having characteristics that violate said design rules in addresses of said memory associated with a marker layer, with said data objects having characteristics that violate said design rules defining object violations.

9. The method as recited in claim 8 further including removing said object violations by identifying memory addresses associated with said object violations and applying a correction function thereto, creating corrected objects and storing a cue concerning said corrected objects in said construction layer, with said cue including said memory addresses associated with said object violations.

10. A method for designing an integrated circuit using a computer having a memory, said method comprising:

mapping said integrated circuit into locations of said memory as multiple production layers with said multiple production layers including a plurality of data objects;

identifying locations in one of said multiple production layers at which to vary data objects at said locations, said data objects having multiple characteristics associated therewith;

varying said data object by changing a subset of said multiple characteristics at said locations, defining varied data objects;

storing information concerning said varied data objects in addresses of said memory associated with a construction layer;

generating a rules file that includes a sequence of commands to determine whether characteristics of said varied data objects satisfy design rules, with the commands associated with said sequence being dependent upon the production layer, among said multiple production layers with which said varied objects are associated and the characteristics of said subset, with said instructions being associated with said sequence are instructions included in CADENCE®

DESIGN FRAMEWORK II®

;

distinguishing said varied data objects having characteristics that violate said design rules from data objects having characteristics that satisfy said design rules and storing said varied data objects having characteristics that violate said design rules in addresses of said memory associated with a marker layer, with said data objects having characteristics that violate said design rules defining object violations; and

removing said object violations by identifying memory addresses associated with said object violations and applying a correction function thereto, creating corrected objects and storing information concerning said corrected objects in addresses of said memory associated with said construction layer.

11. The method as recited in claim 10 wherein distinguishing said varied data objects further includes identifying varied data objects having characteristics that satisfy said design rules, defining acceptable data objects, and storing said acceptable data objects in addresses of said memory associated with said one production layer.

12. The method as recited in claim 10 wherein varying said data object further includes placing a data object at said locations with a different data object.

13. The method as recited in claim 10 wherein varying said characteristics further includes removing said data object at said locations.

14. The method as recited in claim 10 wherein varying said characteristics further includes modifying said data object at said locations.

15. A computer system to design an integrated circuit, said system comprising:

a processor;

a memory in data communication with said processor,

a display in data communication with said processor and said memory, with said memory including a computer-readable medium having a computer-readable program embodied therein, said computer-readable program including a first set of instructions to map said integrated circuit into locations of said memory as multiple production layers with said multiple production layers including a plurality of data objects, a second set of instructions to identify locations in one of said multiple production layers at which to vary data object characteristics at said locations, a third set of instructions to vary said characteristics at said locations, defining varied data objects, a fourth set of instructions to store information concerning said varied data objects in addresses of said memory associated with a construction layer, a fifth set of instructions to generate a rules file that includes a sequence of commands to determine whether characteristics of said varied data objects satisfy design rules, with the commands associated with said sequence being dependent upon the production layer, among said multiple production layers with which said varied data objects are associated and the characteristics varied, and a sixth set of instructions to distinguish said varied data objects having characteristics that violate said design rules from data objects having characteristics that satisfy said design rules.

16. The system as recited in claim 15 wherein said sixth set of instructions further includes a subroutine to identify varied data objects having characteristics that violate, defining failed objects, and storing data concerning said failed data objects at memory addresses in said memory associated with a marker layer, with said data including addresses in said memory where said failed data objects are stored.

17. The system as recited in claim 15 wherein said sixth set of instructions further includes a subroutine to identify varied data objects having characteristics that satisfy said design rules, defining acceptable data objects, and storing said acceptable data objects in addresses of said memory associated with a production layer.

18. A computer product having a computer-readable medium that contains a program to design an integrated circuit on a computer having a memory, said computer product comprising:

computer code to map said integrated circuit into locations of said memory as multiple production layers with said multiple production layers including a plurality of data objects;

computer code to identify locations in one of said multiple production layers at which to vary data object characteristics;

computer code to vary said data object characteristics at said locations, defining varied data objects;

computer code to store information in said memory concerning said varied data objects at addresses in said memory associated with a construction layer;

computer code to generate a rules file that includes a sequence of commands to determine whether characteristics of said varied data objects satisfy design rules, with the commands associated with said sequence being dependent upon the production layer, among said multiple production layers with which said varied objects are associated and characteristics that are varied; and

computer code to distinguish said varied data objects having characteristics that violate said design rules from data objects having characteristics that satisfy said design rules.

19. The computer product as recited in claim 18 wherein said code to distinguish said varied data objects further includes code to identify varied data objects having characteristics that violate said design rules, defining failed data objects, and storing data concerning said failed data objects at addresses in said memory associated with a marker layer, with said data including addresses in said memory where said varied data objects are stored.

20. The computer product as recited in claim 18 wherein said code to distinguish said varied data objects further includes code to identify varied data objects having characteristics that satisfy said design rules, defining acceptable data objects, end code to store said acceptable data objects in addresses of said memory associated with a production layer.