Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits
First Claim
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1. A method for a first party to fabricate a semiconductor device, comprising:
- receiving a sign-off prototype, the sign-off prototype generated by;
defining a physical design of a circuit while tracking an error in prediction of a timing value associated with one or more nets in the circuit;
determining a physical placement level of the circuit when the error in prediction of the timing value satisfies a predetermined threshold; and
generating the sign-off prototype from the physical placement level of the circuit when the error in prediction of the timing value satisfies a predetermined threshold wherein generating said sign-off prototype is performed without using a physical design tool; and
after receiving the sign-off prototype, the first party performing;
generating a second physical design of the circuit from the sign-off prototype;
generating a GDS file from the second physical design;
having a mask set generated from the GDS file; and
having the semiconductor device fabricated using the mask set.
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Abstract
Methods and apparatus for a physical “sign-off” prototype tool that includes a prototype tool that generates a physical prototype for a design and a optimization tool that provides a designer with the option to further optimize the physical prototype before signing off on the design. In either situation, the “sign-off” prototype provides a forward prediction of the area, timing and performance of the final GDS of the design generated by a physical implementation tool.
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Citations
34 Claims
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1. A method for a first party to fabricate a semiconductor device, comprising:
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receiving a sign-off prototype, the sign-off prototype generated by;
defining a physical design of a circuit while tracking an error in prediction of a timing value associated with one or more nets in the circuit;
determining a physical placement level of the circuit when the error in prediction of the timing value satisfies a predetermined threshold; and
generating the sign-off prototype from the physical placement level of the circuit when the error in prediction of the timing value satisfies a predetermined threshold wherein generating said sign-off prototype is performed without using a physical design tool; and
after receiving the sign-off prototype, the first party performing;
generating a second physical design of the circuit from the sign-off prototype;
generating a GDS file from the second physical design;
having a mask set generated from the GDS file; and
having the semiconductor device fabricated using the mask set. - View Dependent Claims (2, 3, 4, 5, 6)
(a) quadrisectioning the physical design into bins;
(b) localizing placement of cells and wires of the physical design into the bins;
(c) creating a profile of the wire lengths in each of the bins;
(d) calculating a plurality of errors in a prediction of timing values from the profile of the wire lengths for each bin respectively;
(e), comparing each of the plurality of errors in the prediction of the timing values with the predetermined threshold to determine if the timing value satisfies the predetermined threshold; and
either;
further quadrisectioning the physical design and repeating (b through e);
orgenerating an interrupt if all of the plurality of errors in the prediction of the timing values for each of the bins satisfy the predetermined threshold.
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7. A semiconductor device manufactured by a first party by:
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receiving a sign-off prototype, the sign-off prototype generated by;
defining a physical design of a circuit while tracking an error in prediction of a timing value associated with one or more nets in the circuit;
determining a physical placement level of the circuit when the error in prediction of the timing value satisfies a predetermined threshold; and
generating the sign-off prototype from the physical placement level of the circuit when the error in prediction of the timing value satisfies a predetermined threshold wherein generating said sign-off prototype is performed without using a physical design tool; and
after receiving the sign-off prototype, the first party performing;
generating a second physical design of the circuit from the sign-off prototype, generating a GDS file from the second physical design;
having a mask set generated from the GDS file, andhaving the semiconductor device fabricated using the mask set. - View Dependent Claims (8, 9, 10, 11, 12)
(a) quadrisectioning the physical design into bins;
(b) localizing placement of cells and wires of the physical design into the bins;
(c) creating a profile of the wire lengths in each of the bins;
(d) calculating a plurality of errors in a prediction of timing values from the profile of the wire lengths for each bin respectively;
(e) comparing each of the plurality of errors in the prediction of the timing values with the predetermined threshold to determine if the timing value satisfies the predetermined threshold; and
either;
further quadrisectioning the physical design and repeating (b through e);
orgenerating an interrupt if all of the plurality of errors in the prediction of the timing values for each of the bins satisfy the predetermined threshold.
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11. The semiconductor device of claim 7, wherein the receiving the sign-off prototype further comprises receiving the sign-off prototype from a second party.
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12. The semiconductor device of claim 11, wherein generating the second physical design of the circuit from the sign-off prototype further comprises performing additional interactive optimization on the sign-off prototype after receiving the sign-off prototype so the second party can collaborate in resolving problems identified in the sign-off prototype.
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13. A method of performing a design of a circuit, comprising:
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accessing a gate level design for said circuit;
creating a physical prototype from said gate level design, said creating of a physical prototype includes predicting of timing for said circuit and tracking an error in said predicting of timing wherein creating said physical prototype is performed without using a physical design tool; and
creating a physical design for said circuit, said creating of said physical design includes placing and routing elements of said circuit, said creating of a physical prototype is performed prior to said creating of said physical design. - View Dependent Claims (14, 15, 16, 17, 18, 19)
said step of creating a physical design is performed using a physical design tool.
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15. A method according to claim 13, wherein said creating of said physical prototype comprises:
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localizing placement of cells and wires;
creating a profile of wire lengths;
calculating an error in a prediction of a timing value from said profile of said wire lengths;
comparing said error in said prediction with a predetermined threshold; and
performing further placement if said error does not satisfy said predetermined threshold.
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16. A method according to claim 13, wherein said creating of said physical prototype comprises:
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defining a representation of said circuit based on said gate level design;
quadrisectioning said representation into bins;
localizing placement of cells and wires of said representation into said bins;
creating a profile of wire lengths in each of said bins;
calculating a plurality of errors in a prediction of timing values from said profile of said wire lengths for each bin respectively;
comparing each of said plurality of errors in said prediction of said timing values with a predetermined threshold; and
if said error does not satisfy said predetermined threshold, further quadrisectioning said representation and repeating said steps of localizing, creating, calculating and comparing.
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17. A method according to claim 13, wherein said creating of said physical prototype further comprises analyzing congestion and power for said physical prototype.
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18. A method according to claim 13, further comprising:
generating a GDS file from said physical design.
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19. A method according to claim 13, further comprising:
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generating a GDS file from said physical design;
having a mask set generated from the GDS file; and
having the semiconductor device fabricated using the mask set.
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20. A method of performing a design of a circuit, comprising:
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accessing a gate level design for said circuit;
creating a physical prototype from said gate level design, said creating of a physical prototype includes predicting of timing for said circuit wherein creating said physical prototype is performed without using a physical design tool; and
providing said physical prototype for a physical design process so that a physical design can be created for said circuit including placing and routing elements of said circuit, said creating of a physical prototype is performed prior to said step of providing. - View Dependent Claims (21, 22, 23, 24)
said step of providing includes providing said physical prototype to a physical design tool.
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22. A method according to claim 20, wherein said creating of said physical prototype comprises:
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localizing placement of cells and wires;
creating a profile of wire lengths;
calculating an error in a prediction of a timing value from said profile of said wire lengths;
comparing said error in said prediction with a predetermined threshold; and
performing further placement if said error does not satisfy said predetermined threshold.
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23. A method according to claim 20, wherein said creating of said physical prototype comprises:
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defining a representation of said circuit based on said gate level design;
quadrisectioning said representation into bins;
localizing placement of cells and wires of said representation into said bins;
creating a profile of wire lengths in each of said bins;
calculating a plurality of errors in a prediction of timing values from said profile of said wire lengths for each bin respectively;
comparing each of said plurality of errors in said prediction of said timing values with a predetermined threshold; and
if said error does not satisfy said predetermined threshold, further quadrisectioning said representation and repeating said steps of localizing, creating, calculating and comparing.
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24. A method according to claim 20, wherein said creating of said physical prototype further comprises analyzing congestion and power for said physical prototype.
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25. A computer-readable medium including computer code configured to perform the design of an integrated circuit, the computer code configures to perform a method comprising:
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accessing a gate level design for said circuit;
creating a physical prototype from said gate level design, said creating of a physical prototype includes predicting of timing for said circuit wherein creating said physical prototype is performed without using a physical design tool; and
providing said physical prototype for a physical design process so that a physical design can be created for said circuit including placing and routing elements of said circuit, said creating of a physical prototype is performed prior to said step of providing. - View Dependent Claims (26, 27, 28, 29)
said step of providing includes providing said physical prototype to a physical design tool.
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27. A computer-readable medium according to claim 25, wherein said creating of said physical prototype comprises:
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localizing placement of cells and wires;
creating a profile of wire lengths;
calculating an error in a prediction of a timing value from said profile of said wire lengths;
comparing said error in said prediction with a predetermined threshold; and
performing further placement if said error does not satisfy said predetermined threshold.
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28. A computer-readable medium according to claim 25, wherein said creating of said physical prototype comprises:
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defining a representation of said circuit based on said gate level design;
quadrisectioning said representation into bins;
localizing placement of cells and wires of said representation into said bins;
creating a profile of wire lengths in each of said bins;
calculating a plurality of errors in a prediction of timing values from said profile of said wire lengths for each bin respectively;
comparing each of said plurality of errors in said prediction of said timing values with a predetermined threshold; and
if said error does not satisfy said predetermined threshold, further quadrisectioning said representation and repeating said steps of localizing, creating, calculating and comparing.
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29. A computer-readable medium according to claim 25, wherein said creating of said physical prototype further comprises analyzing congestion and power for said physical prototype.
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30. A computer system configured to perform the design of a circuit, the computer system comprising:
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means for accessing a gate level design for said circuit;
means for creating a physical prototype from said gate level design, said creating of a physical prototype includes predicting of timing for said circuit wherein creating said physical prototype is performed without using a physical design tool; and
means for providing said physical prototype for a physical design process so that a physical design can be created for said circuit including placing and routing elements of said circuit, said creating of a physical prototype is performed prior to said step of providing. - View Dependent Claims (31, 32, 33, 34)
said means for providing includes providing said physical prototype to a physical design tool.
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32. A computer system according to claim 30, wherein said means for creating of said physical prototype comprises:
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means for localizing placement of cells and wires;
means for creating a profile of wire lengths;
means for calculating an error in a prediction of a timing value from said profile of said wire lengths;
means for comparing said error in said prediction with a predetermined threshold; and
means for performing farther placement if said error does not satisfy said predetermined threshold.
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33. A computer system according to claim 30 wherein said means for creating of said physical prototype comprises:
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means for defining a representation of said circuit based on said gate level design;
means for quadrisectioning said representation into bins;
means for localizing placement of cells and wires of said representation into said bins;
means for creating a profile of wire lengths in each of said bins;
means for calculating a plurality of errors in a prediction of timing values from said profile of said wire lengths for each bin respectively;
means for comparing each of said plurality of errors in said prediction of said timing values with a predetermined threshold; and
means for, if said error does not satisfy said predetermined threshold, further quadrisectioning said representation and repeating said steps of localizing, creating, calculating and comparing.
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34. A computer system according to claim 30, wherein said means for creating of said physical prototype further comprises means for analyzing congestion and power for said physical prototype.
Specification