Device parameter and gate performance simulation based on wafer image prediction

• US 6,775,818 B2
• Filed: 08/20/2002
• Issued: 08/10/2004
• Est. Priority Date: 08/20/2002
• Status: Expired due to Fees

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Callan, Neal, Strelkova, Nadya, Taravade, Kunal
• Primary Examiner(s): DO, THUAN V
• Application Number:
  US10/223,931
• Publication Number:
  US 20040040000A1
• Time in Patent Office: 721 Days
• Field of Search: 703/14, 703/13, 716/19, 716/20, 716/21, 385/24
• US Class Current: 716/53
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A circuit, gate, or device parameter simulation includes data on the initial conditions of manufacture, including illumination conditions on a stepper, material parameters for processing conditions, and chip layout. Optical effects and processing tolerances may be accounted for in the simulation of the final device performance characteristics. The circuit, gate, or device parameter simulation may incorporate optical proximity code software. Simulated active and passive components are generated by the circuit, gate, or device parameter simulation from the simulated patterned layers on the substrate. Feedback may be provided to the circuit, gate, or device parameter simulation to optimize performance.

Claims

1. A method for simulating a circuit, comprising the steps of:

receiving processing condition information;

simulating an integrated circuit layer structure on a substrate through the processing condition information by incorporating lithographic imaging effects;

simulating electrical characteristics of active and passive components from the simulated integrated circuit layer structure by including the lithographic imaging effects; and

simulating circuit performance from the simulated active and passive components to generate an output.

2. The method for simulating a circuit of claim 1, wherein the processing condition information includes lithographic processing data.

3. The method for simulating a circuit of claim 2, wherein the lithographic processing data includes illumination conditions on a stepper lens, material parameters from processing conditions, and chip layout.

4. The method for simulating a circuit of claim 1, wherein the step of simulating an integrated circuit layer structure includes repeating a step of simulating a layer on a substrate.

5. The method for simulating a circuit of claim 1, further comprising the step of comparing an output of the step of simulating circuit performance from the simulated active and passive components with an output from an earlier circuit simulation in which non-identical processing data is used.

6. The method for simulating a circuit of claim 1, further comprising the step of comparing an output of the step of simulating circuit performance from the simulated active and passive components to generate an output with stored data representing benchmark data.

7. The method for simulating a circuit of claim 1, further comprising the step of simulating parasitic capacitances and inductances before the step of simulating circuit performance.

8. The method for simulating a circuit of claim 1, further comprising the step of simulating electromagnetic interference effects before the step of simulating circuit performance.

9. The method for simulating a circuit of claim 1, wherein the step of simulating an integrated circuit layer structure on a substrate includes simulating critical dimensions of various layers used in processing.

10. The method for simulating a circuit of claim 1, wherein the step of simulating active and passive components includes performing Boolean operations on the intersections of layers to define active components.

11. The method for simulating a circuit of claim 10, wherein the active components include NMOS and PMOS transistors.

12. The method for simulating a circuit of claim 1, wherein the step of simulating an integrated circuit layer structure on a substrate includes simulating an aerial image.

13. The method for simulating a circuit of claim 12, wherein the step of simulating an integrated circuit layer structure on a substrate further includes simulating a resist image.

14. A computer program of instructions storable on a medium readable by an information handling system for simulating electrical characteristics through the execution of a method, said method comprising steps of:

receiving processing condition information;

simulating an integrated circuit layer structure on a substrate through the processing condition information; and

simulating electrical characteristics of active and passive components based on wafer image prediction from the simulated integrated circuit layer structure.

15. The computer program of instructions storable on a medium readable by an information handling system for simulating electrical characteristics through the execution of steps of claim 14, wherein said method further comprising the step of simulating circuit performance from simulated active and passive components corresponding to the simulated electrical characteristics.

16. The computer program of instructions storable on a medium readable by an information handling system for simulating electrical characteristics through the execution of steps of claim 14, wherein the computer program has a first portion which includes code for the step of simulating an integrated circuit layer structure and a second portion which includes code for the step of simulating electrical characteristics based upon simulated patterned layers.

17. The computer program of instructions storable on a medium readable by an information handling system for simulating electrical characteristics through the execution of steps of claim 16, wherein the first portion is a first software module and the second portion is a second software module.

18. The computer program of instructions storable on a medium readable by an information handling system for simulating electrical characteristics through the execution of steps of claim 17, wherein the computer program further comprising a third portion that interfaces both the first portion and the second portion.

19. The computer program of instructions storable on a medium readable by an information handling system for simulating electrical characteristics through the execution of steps of claim 16, wherein the first portion is an optical proximity correction module.

20. The computer program of instructions storable on a medium readable by an information handling system for simulating electrical characteristics through the execution of steps of claim 16, wherein the second portion is an electronic design automation module.

21. The computer program of instructions storable on a medium readable by an information handling system for simulating electrical characteristics through the execution of steps of claim 14, wherein said method further comprising the step of establishing active components and passive components to form a circuit model after the step of simulating an integrated circuit layer structure on a substrate through the processing condition information.

22. A system for simulating the performance of a circuit using device parameter and gate performance simulation based on wafer image prediction, comprising:

a processor which performs a simulation of electrical characteristics of active and passive components of a circuit using device parameter and gate performance based on wafer image prediction;

an input device coupled to the processor; and

a display device coupled to the processor.

23. The system for simulating the performance of a circuit using device parameter and gate performance simulation based on wafer image prediction of claim 22, wherein the display device has a graphical user interface for manipulating elements of the circuit.

24. The system for simulating the performance of a circuit using device parameter and gate performance simulation based on wafer image prediction of claim 22, wherein the simulation includes Boolean operations for parallel conducting or semiconductive, electrically isolated layers that are separated by an insulating layer.

25. The system for simulating the performance of a circuit using device parameter and gate performance simulation based on wafer image prediction of claim 22, wherein the simulation incorporates an optical proximity correction module.

26. The system for simulating the performance of a circuit using device parameter and gate performance simulation based on wafer image prediction of claim 22, wherein the wafer image prediction includes an aerial image that provides a map of developed portions of a resist layer.