Semiconductor device and fabrication method thereof

• US 6,777,254 B1
• Filed: 07/05/2000
• Issued: 08/17/2004
• Est. Priority Date: 07/06/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Arai, Yasuyuki, Koyama, Jun, Yamazaki, Shunpei
• Primary Examiner(s): Booth, Richard A.
• Application Number:
  US09/610,217
• Time in Patent Office: 1,504 Days
• Field of Search: 438/30, 438/151-166
• US Class Current: 438/30
• CPC Class Codes: G02F 1/13306 Circuit arrangements or driving methods for the control of single liquid crystal cells G02F1/132, G02F1/133382 take precedence
• CPC Class Codes: G02F 1/133345 Insulating layers G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence
• CPC Class Codes: G02F 1/13394 spacers regularly patterned on the cell subtrate, e.g. walls, pillars G02F1/133377 takes precedence
• CPC Class Codes: G02F 1/13396 Spacers having different sizes
• CPC Class Codes: G02F 1/13398 Spacer materials; Spacer properties
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/13624 having more than one switching element per pixel
• CPC Class Codes: G02F 1/136245 having complementary transistors
• CPC Class Codes: G02F 1/136277 formed on a semiconductor substrate, e.g. of silicon
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02208 the precursor containing a compound comprising Si
• CPC Class Codes: H01L 21/02266 deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02532 : Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02592 : amorphous
• CPC Class Codes: H01L 21/0262 : Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 : Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02667 : Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/0273 : characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/3065 : Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 : characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 27/12 : the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 : with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1248 : with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1251 : comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1274 : using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
• CPC Class Codes: H01L 27/1288 : employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/167 : further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66742 : Thin film unipolar transistors
• CPC Class Codes: H01L 29/66757 : Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/7833 : with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/78621 : with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78672 : Polycrystalline or microcrystalline silicon transistor
• CPC Class Codes: H01L 29/78675 : with normal-type structure, e.g. with top gate
• CPC Class Codes: Y10S 438/919 : Compensation doping

Abstract

A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, in an inter-layer insulation film disposed on the insolation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Claims

1. A method of fabricating a semiconductor device comprising:

forming a first semiconductor island and a second semiconductor island and a third semiconductor island over a substrate;

forming a first low concentration n-type impurity region and a second low concentration n-type impurity region and a third low concentration n-type impurity region respectively in said first semiconductor island and said second semiconductor island and said third semiconductor island by introducing a first impurity imparting n-type into said first low concentration n-type impurity region and said second low concentration n-type impurity region and said third low concentration n-type impurity region;

forming a first photoresist and a second photoresist and a third photresist respectively over said first semiconductor island and said second semiconductor island and said third semiconductor island so that said first photoresist partially overlaps with said first low concentration n-type impurity region and said second photoresist partially overlaps with said second low concentration n-type impurity region and said third photoresist partially overlaps with said third low concentration n-type impurity region;

forming a first high concentration n-type impurity region and a second high concentration n-type impurity region and a third high concentration n-type impurity region respectively in said first semiconductor island and said second semiconductor island and said third semiconductor island by introducing a second impurity imparting n-type into a first part of each of said first low concentration n-type impurity region and said second low concentration n-type impurity region and said third low concentration n-type impurity region using said first photoresist and said second photoresist and said third photoresist as masks to leave behind second parts provided under said masks in said first low concentration n-type impurity region and said second low concentration n-type impurity region and said third low concentration n-type impurity region as they are; and

introducing impurities imparting p-type into said second low concentration n-type impurity region and said second high concentration n-type impurity region to change said second low concentration n-type impurity region and said second high concentration n-type impurity region to a p-type impurity region,

wherein concentration of said second impurity is higher than concentration of said first impurity,

wherein said first semiconductor island is formed in an n-channel thin film transistor of a driving circuit,

wherein said second semiconductor island is formed in a p-channel thin film transistor of said driving circuit, and

wherein said third semiconductor island is formed in a pixel thin film transistor.

2. A method according to claim 1 further comprising:

forming a protective insulation film comprising an inorganic insulating material over said n-channel thin film transistor of said driving circuit, said pixel thin film transistor and said p-channel thin film transistor;

forming an inter-layer insulation film comprising an organic insulating material in contact with said protective insulation film; and

forming over said inter-layer insulating film a pixel electrode having a light reflecting surface and connected to said pixel thin film transistor.

3. A method according to claim 2, wherein, said p-type impurity region is formed in said p channel thin film transistor of said driving circuit in a selected region of said second semiconductor island after said step of forming said protective insulation film comprising an inorganic insulating material, over a gate electrode of said p channel thin film transistor, and an offset region is formed between a channel formation region of said p channel thin film transistor and said p type impurity region.

4. A method according to claim 2 wherein said protective insulation film comprises a material selected from the group consisting of silicon oxide, silicon oxide nitride and silicon nitride.

5. A method according to claim 2 wherein said protective insulation film has a thickness of 100 to 200 nm.

6. A method according to claim 2 wherein said inter-layer insulation film has a mean thickness of 1.0 to 2.0 μ

m.

7. A method according to claim 2 wherein said inter-layer insulation film comprises a material selected from the group consisting of polyimide, acryl, polyamide, polyimidamide and benzocyclobutene.

8. A method according to claim 2 wherein said pixel electrode comprises a Ti film and an Al film.

9. A method according to claim 1 wherein said p channel thin film transistor has a single drain structure.

10. A method according to claim 1 wherein said first low concentration n-type impurity region of said first semiconductor island formed in said n channel thin film transistor of said driving circuit have a length of 1.0 to 4.0 μ

m.

11. A method according to claim 1 wherein said third low concentration n-type impurity region of said third semiconductor island formed in said pixel thin film transistor have a length of 0.5 to 4.0 μ

m.

12. A method according to claim 1 wherein said first and second and third semiconductor islands have a thickness of 25 to 80 μ

n.

13. A method according to claim 1 wherein said driving circuit comprises a circuit selected from the group consisting of a shift register circuit, a level shifter circuit, a buffer circuit and sampling circuit.