Circuit board

• US 6,777,620 B1
• Filed: 10/11/2000
• Issued: 08/17/2004
• Est. Priority Date: 12/02/1999
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Abe, Takashi
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): PATEL, ISHWARBHAI B
• Application Number:
  US09/685,771
• Time in Patent Office: 1,406 Days
• Field of Search: 174/250, 174/255, 174/256, 174/259, 174/260, 174/261, 174/262, 174/263, 174/264, 361/760, 361/792, 361/793, 361/794, 361/752, 361/753, 361/767, 361/796, 361/800, 361/808, 361/818, 361/820
• US Class Current: 174/255
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/0218 by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence

Abstract

A substrate of the present invention includes pads which are provided on the surface of said substrate; and surface layers which are kept to the ground potential and cover the surface of said substrate except said pads and their peripheral. Another substrate of the present invention includes a part of circuit which is provided on the surface of said substrate; and a surface layers which are kept to the ground potential and cover the surface of said substrate except said part of circuit and its peripheral.

Claims

1. A substrate comprising:

pads which are provided on the surface of said substrate;

surface layers which are kept to the ground potential and cover the surface of said substrate except said pads and their narrow periphery, wherein said surface layers include a top main surface and a bottom main surface; and

conductive elements which electronically connect said top main surface and said bottom main surface and cover an entire side of said substrate with said top main surface and said bottom main surface.

2. The substrate as claimed in claim 1, further comprising:

vias which electronically connects said top main surface and said bottom main surface.

3. The substrate as claimed in claim 2, wherein said vias are provided on the side portion of said substrate.

4. The substrate as claimed in claim 1, wherein said surface layers further includes a side layer which electronically connects said top main surface and said bottom main surface.

5. The substrate as claimed in claim 1, wherein said surface layers includes six surface layers.

6. The substrate as claimed in claim 1, further comprising a signal layer which is provided between said top main surface and said bottom main surface, and has a pattern which is connected to at least one of said pads.

7. The substrate as claimed in claim 1, wherein an interval between said pad and said surface layer is defined to prevent said pad form short-circuiting.

8. A substrate comprising:

a part of circuit which is provided on the surface of said substrate;

surface layers which are kept to the ground potential and cover the surface of said substrate except said part of circuit and its narrow periphery, wherein said surface layers include a top main surface and a bottom main surface; and

conductive elements which electronically connect said top main surface and said bottom main surface and cover an entire side of said substrate with said top main surface and said bottom main surface.

9. The substrate as claimed in claim 8, further comprising:

vias which electronically connects said top main surface and said bottom main surface.

10. The substrate as claimed in claim 9, wherein said vias are provided on the side portion of said substrate.

11. The substrate as claimed in claim 8, wherein said surface layers further include a side layer which electronically connects said top main surface and said bottom main surface.

12. The substrate as claimed in claim 8, wherein said surface layers include six surface layers.

13. The substrate as claimed in claim 8, further comprising a signal layer which is provided between said top main surface and said bottom main surface, and has a pattern which is connected to said part of circuit.

14. The substrate as claimed in claim 8, wherein an interval between said part of circuit and said surface layer is defined to prevent said part of circuit from short-circuiting.