CMOS active pixel with reset noise reduction

• US 6,777,660 B1
• Filed: 02/04/2002
• Issued: 08/17/2004
• Est. Priority Date: 02/04/2002
• Status: Expired due to Term

• Current Assignee: SMAL Camera Technologies
• Original Assignee: SMAC Technologies Pty., Ltd.
• Inventors: Lee, Hae-Seung
• Primary Examiner(s): Luu, Thanh X.
• Assistant Examiner(s): Sohn, Seung C
• Application Number:
  US10/067,554
• Time in Patent Office: 925 Days
• Field of Search: 250/208.1, 250/206, 250/200, 250/214.AG, 250/214.A, 250/214.R, 348/308, 348/300, 348/241, 330/308, 330/250
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 31/02016 Circuit arrangements of general character for the devices
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A CMOS image sensor array has rows and columns of active pixels. In addition, there are one or more column lines each cooperating with the active pixels in the respective columns. Each active pixel has an output connected to a column line. Each active pixel includes a photodiode that produces a signal proportional to incident light intensity. The proportional signal is applied to the active pixel output if the column select and row select are appropriately set. In addition, each active pixel has a reset transistor for resetting the active pixel. Each reset transistor has a gate and first and second terminals. A reset voltage is applied to the gate of each reset transistor to cause a reset.

The CMOS image sensor array also has one or more amplifiers. Each amplifier has a first input connected to a different column line. Each amplifier provides a negative feedback output to the first node of each reset transistor of the active pixels for the respective cooperating column line. An reset reference voltage is applied to a second input of each amplifier to adjust the negative feedback to adjust the voltage at the second node of each reset transistor to a desired reset voltage. The second node of each reset transistor cooperates with the first input of the respective amplifier for the column.

Claims

1. An image sensor comprising:

a plurality of pixels each having an output, each pixel including;

a first circuit that produces a signal proportional to incident light intensity, said first circuit being connected to supply said proportional signal to said pixel output,

a select node connected to receive a select signal for selecting said pixel from said plurality of pixels, and

a reset transistor for resetting said pixel;

an amplifier having;

a first input for receiving said outputs of said pixels, and

an output connected to said pixels to be actively coupled to said reset transistors during a pixel reset phase to provide a negative feedback signal to a selected pixel during said pixel reset phase; and

a reset reference voltage source connected to apply a reset reference voltage signal to said amplifier to provide a voltage reference for controlling reset of said pixels.

2. The image sensor of claim 1 wherein said amplifier further includes a second input receiving said reset reference voltage signal.

3. The image sensor of claim 2 wherein said reset transistor includes a gate and first and second terminals, said first terminal connected to receive said negative feedback signal to adjust said second terminal'"'"'s voltage to a selected reset voltage.

4. The image sensor of claim 3 wherein said reset reference voltage source signal is selected to control said voltage at said second reset transistor terminal to be about V_T−

Δ

V below a reset voltage applied at said gate terminal of said reset transistor, where V_T is a threshold voltage that is characteristic of said reset transistor, and Δ

V is selected to maintain said reset transistor in a subthreshold region of operation during a steady state phase of pixel reset.

5. The image sensor of claim 4 wherein said selected Δ

V is greater than about one hundred millivolts.

6. The image sensor of claim 4 wherein said select node of each said pixel comprises a terminal of a row select transistor that is coupled to said first input of said amplifier.

7. The image sensor of claim 6 wherein each said pixel further comprises a source follower transistor coupled between said second terminal of said reset transistor and a terminal of said row select transistor.

8. The image sensor of claim 3 wherein said first circuit comprises a photocircuit.

9. The image sensor of claim 8 wherein said amplifier comprises a differential amplifier including a first differential amplifier input transistor connected to receive said first amplifier input and a second differential amplifier input transistor connected to receive said second amplifier input, said first and second differential amplifier input transistors connected to provide a signal to a current mirror circuit that is connected to deliver said negative feedback signal to said reset transistor first terminal.

10. The image sensor of claim 8 wherein said photocircuit includes a photodiode and a capacitance.

11. The image sensor of claim 7 wherein said first circuit is a photocircuit.

12. The image sensor of claim 11 wherein said photocircuit includes a photodiode and a capacitance.

37. The image sensor of claim 1 wherein said image sensor comprises a CMOS-compatible image sensor.

39. The image sensor of claim 1 wherein said pixels comprise active pixels.

13. An image sensor array having rows and columns of pixels, comprising:

at least one column line;

a plurality of pixels each having an output, the outputs of pixels in a column being connected to a common respective column line, each said pixel including;

a first circuit that produces a signal proportional to incident light intensity, said first circuit being connected to supply said proportional signal to said pixel output, and

a reset transistor for resetting said pixel;

at least one amplifier, each said amplifier having a first input coupled to at least one said column line, each said amplifier being connected to provide a negative feedback signal to each said pixel reset transistor of a respective column of pixels during each corresponding pixel reset phase; and

a reset reference voltage source connected to apply a reset reference voltage signal to each said amplifier to provide a voltage reference for controlling reset of said pixels.

14. The image sensor of claim 13 wherein said amplifier further includes a second input for receiving said reset reference voltage signal.

15. The image sensor of claim 14 wherein said reset transistor includes a gate and first and second terminals, said first terminal connected to receive said negative feedback signal to adjust said second terminal'"'"'s voltage to a selected reset voltage.

16. The image sensor of claim 15 wherein said reset reference voltage source signal is selected to control said voltage at said second reset transistor terminal to be about V_T−

Δ

V below a reset voltage applied at said gate terminal of said reset transistor, where V_T is a threshold voltage that is characteristic of said reset transistor, and Δ

V is selected to maintain said reset transistor in a subthreshold region of operation during a steady state phase of pixel reset.

17. The image sensor array of claim 16 wherein said selected Δ

V is greater than about one hundred millivolts.

18. The image sensor array of claim 16 wherein each pixel comprises a row select transistor coupled between said second terminal of said reset transistor and said first input of said amplifier.

19. The image sensor array of claim 18 wherein each pixel further comprises a source follower transistor coupled between said second terminal of said reset transistor and a terminal of said row select transistor.

20. The image sensor array of claim 16 wherein said first circuit of each pixel comprises a photocircuit.

21. The image sensor array of claim 20 wherein said amplifier comprises a differential amplifier including a first differential amplifier input transistor connected to receive said first amplifier input and a second differential amplifier input transistor connected to receive said second amplifier input, said first and second differential amplifier input transistors connected to provide a signal to a current mirror circuit that is connected to deliver said negative feedback signal to said reset transistor first terminal.

22. The image sensor array of claim 20 wherein said photocircuit of each active pixel comprises a photodiode and a capacitance.

23. The image sensor array of claim 19 wherein each said first circuit comprises a photocircuit.

24. The image sensor array of claim 23 wherein each said photocircuit comprises a photodiode and a capacitance.

38. The image sensor array of either of claims 13 or 25 wherein said image sensor array comprises a CMOS-compatible image sensor array.

40. The image sensor array or either of claims 13 or 25 wherein said pixels comprise active pixels.

25. An image sensor array having rows and columns of pixels, comprising:

at least one row line;

a plurality of pixels each having an output, the outputs of pixels in a row being connected to a common respective row line, each said pixel including;

a first circuit that produces a current proportional to incident light intensity, said first circuit being connected to supply said proportional current to said pixel output, and

a reset transistor for resetting said pixel;

at least one amplifier, each said amplifier having a first input coupled to at least one said row line, each said amplifier being connected to provide a negative feedback signal to each said pixel reset transistor of a respective row of pixels during each corresponding pixel reset phase; and

a reset reference voltage source connected to apply a reset reference voltage signal to each said amplifier to provide a voltage reference for controlling reset of said pixels.

26. The image sensor of claim 25 wherein said amplifier further includes a second input for receiving said reset reference voltage signal.

27. The image sensor of claim 26 wherein said reset transistor includes a gate and first and second terminals, said first terminal connected to receive said negative feedback signal to adjust said second terminal'"'"'s voltage to a selected reset voltage.

28. The CMOS image sensor of claim 27 wherein said reset reference voltage source signal is selected to control said voltage at said second terminal to be about V_T−

Δ

V below a reset voltage applied at said gate terminal of said reset transistor, where V_T is a threshold voltage that is characteristic of said reset transistor, and Δ

V is selected to maintain said reset transistor in a subthreshold region of operation during a steady state phase of pixel reset.

29. The image sensor array of claim 28 wherein said selected Δ

V is greater than about one hundred millivolts.

30. The image sensor array of claim 28 wherein each pixel comprises a column select transistor coupled between said second terminal of said reset transistor and said first input of said amplifier.

31. The image sensor array of claim 30 wherein each pixel further comprises a source follower transistor coupled between said second terminal of said reset transistor and a terminal of said column select transistor.

32. The image sensor array of claim 28 wherein said first circuit of each pixel comprises a photocircuit.

33. The image sensor array of claim 32 wherein said amplifier comprises a differential amplifier including a first differential amplifier input transistor connected to receive said first amplifier input and a second differential amplifier input transistor connected to receive said second amplifier input, said first and second differential amplifier input transistors connected to provide a signal to a current mirror circuit that is connected to deliver said negative feedback signal to said reset transistor first terminal.

34. The image sensor array of claim 32 wherein said photocircuit of each pixel comprises a photodiode and a capacitance.

35. The image sensor array of claim 31 wherein each said first circuit comprises a photocircuit.

36. The image sensor array of claim 35 wherein each said photocircuit comprises a photodiode and a capacitance.