Antiparallel magnetoresistive memory cells

• US 6,777,730 B2
• Filed: 08/29/2002
• Issued: 08/17/2004
• Est. Priority Date: 08/31/2001
• Status: Expired due to Term

• Current Assignee: NVE Corporation
• Original Assignee: NVE Corporation
• Inventors: Wang, Dexin, Daughton, James M., Pohm, Arthur V.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, LONG K
• Application Number:
  US10/230,474
• Publication Number:
  US 20030048676A1
• Time in Patent Office: 719 Days
• Field of Search: 257/295, 257/310, 257/311, 438/3, 438/257, 365/158, 365/145, 365/154, 365/157, 365/185.07
• US Class Current: 257/295
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 25/00 Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: H01F 10/3254 the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
• CPC Class Codes: H01F 10/3272 by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets
• CPC Class Codes: H01F 10/329 Spin-exchange coupled multilayers wherein the magnetisation of the free layer is switched by a spin-polarised current, e.g. spin torque effect
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

A ferromagnetic thin-film based digital memory having a plurality of bit structures electrically interconnected with information storage and retrieval circuitry that avoids information loss in one bit structure because of operating the others through this circuitry. Each of these bit structures formed of a relative orientation maintenance intermediate layer having two major surfaces on opposite sides thereof with a pair of memory films of an anisotropic ferromagnetic material each on a corresponding one of said relative orientation maintenance intermediate layer major surfaces. The relative orientation maintenance intermediate layer is of a material and a selected thickness so as to maintain magnetizations of said memory films oriented in substantially opposite directions. Interconnection electrodes pairs are each in electrically conductive contact with a corresponding one of the bit structures on substantially opposite sides thereof near or at substantially opposite edges of the relative orientation maintenance intermediate layer major surface. A magnetization reference direction layer able to maintain relatively well its magnetization orientation can be provided across a nonmagnetic layer from one of the pair of memory films with the nonmagnetic layer being either electrically conductive or insulative.

Claims

1. A ferromagnetic thin-film based digital memory, said memory comprising:

a plurality of bit structures electrically interconnected with information storage and retrieval circuitry, said bit structures comprising;

a relative orientation maintenance intermediate layer having two major surfaces on opposite sides thereof; and

a pair of memory films of an anisotropic ferromagnetic material each on a corresponding one of said relative orientation maintenance intermediate layer major surfaces, said relative orientation maintenance intermediate layer being of a material and a selected thickness so as to maintain magnetizations of said memory films oriented in substantially opposite directions, said pair of memory films having sufficiently similar magnetic moments so as to substantially maintain magnetization orientations thereof despite magnetic fields occurring thereabout due to changes of magnetizations orientations of those said pairs of memory films in other said bit structures in said plurality thereof under direction of said information storage and retrieval circuitry; and

interconnection electrodes having pairs thereof each in electrically conductive contact with a corresponding one of said bit structures with members in a said interconnection electrode pair contacting a corresponding bit structure being spaced apart from one another and each near or at edges of a said relative orientation maintenance intermediate layer major surface with at least one member of a said interconnection electrode pair being electrically coupled to said information storage and retrieval circuitry.

2. The apparatus of claim 1 further comprising in a said bit structure a nonmagnetic intermediate layer on one of said pair of memory films and across that said memory film from one of said relative orientation maintenance intermediate layer major surfaces, said nonmagnetic intermediate layer having a major surface on a side thereof opposite said pair of memory films, and a magnetization reference layer on said major surface of said nonmagnetic intermediate layer having a substantially fixed magnetization direction.

3. The apparatus of claim 1 further comprising a plurality of transistors electrically interconnected in said information storage and retrieval circuitry so that a said bit structure has a transistor in said plurality of transistors electrically coupled thereto that selectively substantially prevents current in at least one direction along a current path through that said bit structure.

4. The apparatus of claim 1 wherein said bit structures are provided on a substrate and said substrate further comprises a monolithic integrated circuit structure containing electronic circuit components of which at least one is electrically connected to a said bit structure.

5. The apparatus of claim 1 wherein a said bit structure has a length extending between a said pair of interconnection electrodes and a width substantially perpendicular thereto that is smaller in extent than said length, said width being less than about two curling lengths of said separate films from edges thereof substantially perpendicular to said width.

6. The apparatus of claim 2 wherein said nonmagnetic intermediate layer in said bit structure is an electrical conductor.

7. The apparatus of claim 2 wherein said nonmagnetic intermediate layer in said bit structure is an electrical insulator.

8. The apparatus of claim 2 wherein said magnetization reference layer in said bit structure comprises an antiferromagnetic layer positioned at a major surface of a first reference ferromagnetic thin-film layer.

9. The apparatus of claim 8 further comprising a plurality of electrical current conductors each positioned across an insulating layer from a corresponding said bit structure.

10. The apparatus of claim 8 wherein said magnetization reference layer further comprises a second reference ferromagnetic thin-film layer separated from said first reference ferromagnetic thin-film layer by an antiparallel magnetization directing layer forcing magnetizations of said first and second reference ferromagnetic thin-film layers to be oppositely directed.

11. The apparatus of claim 9 wherein said plurality of bit structures are each supported on a substrate and separated from one another by spacer material therebetween, and wherein a magnetic material layer in said magnetization reference layer has a characteristic magnetic property that is maintained below a critical temperature above which such magnetic property is not maintained, said bit structures each having a first interconnection structure providing electrical contact thereto positioned against at least one side thereof, and said plurality of electrical conductors each exhibits sufficient electrical resistance where across from a selected said corresponding bit structure for a sufficient electrical current therethrough to cause substantial heating of said selected corresponding bit structure to raise temperatures thereof to have said magnetic material layer therein approach said critical temperature thereof while being substantially above temperatures of at least an adjacent said bit structure because of sufficient extents of, and smallness of thermal conductivities of, said first interconnection structure positioned against said selected corresponding bit structure and of those portions of said substrate and said spacer material positioned thereabout.

12. The apparatus of claim 1 wherein said pairs of said interconnection electrodes in electrically conductive contact with a corresponding one of said bit structures are on substantially opposite sides thereof near or at substantially opposite edges of a said relative orientation maintenance intermediate layer major surface.

13. The apparatus of claim 1 further comprising a plurality of electrical current conductors each positioned across an insulating layer from a corresponding said bit structure.

14. The apparatus of claim 3 wherein said bit structure having a said transistor in said plurality of transistors electrically coupled thereto has said coupling provided at least in part by one of said pair of said interconnection electrodes in electrically conductive contact therewith.

15. The apparatus of claim 4 wherein said bit structure having a said electronic circuit component electrically coupled thereto has said coupling provided at least in part by one of said pair of said interconnection electrodes in electrically conductive contact therewith.

16. The apparatus of claim 13 wherein said plurality of bit structures are each supported on a substrate and separated from one another by spacer material therebetween, and wherein a magnetic material layer in said magnetization reference layer has a characteristic magnetic property that is maintained below a critical temperature above which such magnetic property is not maintained, said bit structures each having a first interconnection structure providing electrical contact thereto positioned against at least one side thereof, and said plurality of electrical conductors each exhibits sufficient electrical resistance where across from a selected said corresponding bit structure for a sufficient electrical current therethrough to cause substantial heating of said selected corresponding bit structure to raise temperatures thereof to have said magnetic material layer therein approach said critical temperature thereof while being substantially above temperatures of at least an adjacent said bit structure because of sufficient extents of, and smallness of thermal conductivities of, said first interconnection structure positioned against said selected corresponding bit structure and of those portions of said substrate and said spacer material positioned thereabout.

17. A ferromagnetic thin-film based digital memory, said memory comprising:

a plurality of bit structures electrically interconnected with information storage and retrieval circuitry, said bit structures comprising;

a relative orientation maintenance intermediate layer having two major surfaces on opposite sides thereof,

a pair of memory films of an anisotropic ferromagnetic material each on a corresponding one of said relative orientation maintenance intermediate layer major surfaces, said relative orientation maintenance intermediate layer being of a material and a selected thickness so as to maintain magnetizations of said memory films oriented in substantially opposite directions, said pair of memory films having sufficiently similar magnetic moments so as to substantially maintain magnetization orientations thereof despite magnetic fields occurring thereabout due to changes of magnetizations orientations of those said pairs of memory films in other said bit structures in said plurality thereof under direction of said information storage and retrieval circuitry;

a nonmagnetic intermediate layer of an electrically conductive material on one of said pair of memory films and across that said memory film from one of said relative orientation maintenance intermediate layer major surfaces with said nonmagnetic intermediate layer having a major surface on a side thereof opposite said pair of memory films; and

a magnetization reference layer on said major surface of said nonmagnetic intermediate layer having a substantially fixed magnetization direction; and

interconnection electrodes having pairs thereof each in electrically conductive contact with a corresponding one of said bit structures with members in a said interconnection electrode pair contacting a corresponding bit structure being spaced apart from one another and each near or at edges of a said relative orientation maintenance intermediate layer major surface with at least one member of a said interconnection electrode pair being electrically coupled to said information storage and retrieval circuitry.

18. The apparatus of claim 17 further comprising a plurality of transistors electrically interconnected in said information storage and retrieval circuitry so that a said bit structure has a transistor in said plurality of transistors electrically coupled thereto that selectively substantially prevents current in at least one direction along a current path through that said bit structure.

19. The apparatus of claim 17 wherein said bit structures are provided on a substrate and said substrate further comprises a monolithic integrated circuit structure containing electronic circuit components of which at least one is electrically connected to a said bit structure.

20. The apparatus of claim 17 wherein a said bit structure has a length extending between a said pair of interconnection electrodes and a width substantially perpendicular thereto that is smaller in extent than said length, said width being less than about two curling lengths of said separate films from edges thereof substantially perpendicular to said width.

21. The apparatus of claim 17 wherein said magnetization reference layer in a said bit structure comprises an antiferromagnetic layer positioned at a major surface of a first reference ferromagnetic thin-film layer.

22. The apparatus of claim 21 further comprising a plurality of electrical current conductors each positioned across an insulating layer from a corresponding said bit structure.

23. The apparatus of claim 21 wherein said magnetization reference layer further comprises a second reference ferromagnetic thin-film layer separated from said first reference ferromagnetic thin-film layer by an antiparallel magnetization directing layer forcing magnetizations of said first and second reference ferromagnetic thin-film layers to be oppositely directed.

24. The apparatus of claim 22 wherein said plurality of bit structures are each supported on a substrate and separated from one another by spacer material therebetween, and wherein a magnetic material layer in said magnetization reference layer has a characteristic magnetic property that is maintained below a critical temperature above which such magnetic property is not maintained, said bit structures each having a first interconnection structure providing electrical contact thereto positioned against at least one side thereof, and said plurality of electrical conductors each exhibits sufficient electrical resistance where across from a selected said corresponding bit structure for a sufficient electrical current therethrough to cause substantial heating of said selected corresponding bit structure to raise temperatures thereof to have said magnetic material layer therein approach said critical temperature thereof while being substantially above temperatures of at least an adjacent said bit structure because of sufficient extents of, and smallness of thermal conductivities of, said first interconnection structure positioned against said selected corresponding bit structure and of those portions of said substrate and said spacer material positioned thereabout.

25. The apparatus of claim 17 wherein said pairs of said interconnection electrodes in electrically conductive contact with a corresponding one of said bit structures are on substantially opposite sides thereof near or at substantially opposite edges of a said relative orientation maintenance intermediate layer major surface.

26. The apparatus of claim 18 wherein said bit structure having a said transistor in said plurality of transistors electrically coupled thereto has said coupling provided at least in part by one of said pair of said interconnection electrodes in electrically conductive contact therewith.

27. The apparatus of claim 19 wherein said bit structure having a said electronic circuit component electrically coupled thereto has said coupling provided at least in part by one of said pair of said interconnection electrodes in electrically conductive contact therewith.

28. A ferromagnetic thin-film based digital memory, said memory comprising:

a plurality of bit structures electrically interconnected with information storage and retrieval circuitry, said bit structures comprising;

a relative orientation maintenance intermediate layer having two major surfaces on opposite sides thereof; and

a memory film of an anisotropic ferromagnetic material on each of said relative orientation maintenance intermediate layer major surfaces, said relative orientation maintenance intermediate layer being of a material and a selected thickness so as to maintain magnetizations of said memory film, adjacent each of said intermediate layer major surfaces, oriented in substantially opposite directions;

a nonmagnetic intermediate layer of an electrically insulative material on said memory film across from one of said relative orientation maintenance intermediate layer major surfaces with said nonmagnetic intermediate layer having a major surface on a side thereof opposite said memory film; and

a magnetization reference layer on said major surface of said nonmagnetic intermediate layer having a substantially fixed magnetization direction; and

interconnection electrodes having pairs thereof each in electrically conductive contact with a corresponding one of said bit structures with members in a said interconnection electrode pair contacting a corresponding bit structure being spaced apart from one another and each near or at edges of a said relative orientation maintenance intermediate layer major surface with at least one member of a said interconnection electrode pair being electrically coupled to said information storage and retrieval circuitry.

29. The apparatus of claim 28 wherein said memory film at each of said major surfaces of said relative orientation maintenance intermediate layer of at least one of said bit structures is arranged such that there are two separate films with one of said separate films on each of said major surfaces.

30. The apparatus of claim 28 further comprising a plurality of transistors electrically interconnected in said information storage and retrieval circuitry so that a said bit structure has a transistor in said plurality of transistors electrically coupled thereto that selectively substantially prevents current in at least one direction along a current path through that said bit structure.

31. The apparatus of claim 28 wherein said bit structures are provided on a substrate and said substrate further comprises a monolithic integrated circuit structure containing electronic circuit components of which at least one is electrically connected to a said bit structure.

32. The apparatus of claim 29 wherein a said bit structure has a length extending between a said pair of interconnection electrodes and a width substantially perpendicular thereto that is smaller in extent than said length, said width being less than about two curling lengths of said separate films from edges thereof substantially perpendicular to said width.

33. The apparatus of claim 29 wherein said magnetization reference layer in a said bit structure comprises an antiferromagnetic layer positioned at a major surface of a first reference ferromagnetic thin-film layer.

34. The apparatus of claim 33 further comprising a plurality of electrical current conductors each positioned across an insulating layer from a corresponding said bit structure.

35. The apparatus of claim 33 wherein said magnetization reference layer further comprises a second reference ferromagnetic thin-film layer separated from said first reference ferromagnetic thin-film layer by an antiparallel magnetization directing layer forcing magnetizations of said first and second reference ferromagnetic thin-film layers to be oppositely directed.

36. The apparatus of claim 34 wherein said plurality of bit structures are each supported on a substrate and separated from one another by spacer material therebetween, and wherein a magnetic material layer in said magnetization reference layer has a characteristic magnetic property that is maintained below a critical temperature above which such magnetic property is not maintained, said bit structures each having a first interconnection structure providing electrical contact thereto positioned against at least one side thereof, and said plurality of electrical conductors each exhibits sufficient electrical resistance where across from a selected said corresponding bit structure for a sufficient electrical current therethrough to cause substantial heating of said selected corresponding bit structure to raise temperatures thereof to have said magnetic material layer therein approach said critical temperature thereof while being substantially above temperatures of at least an adjacent said bit structure because of sufficient extents of, and smallness of thermal conductivities of, said first interconnection structure positioned against said selected corresponding bit structure and of those portions of said substrate and said spacer material positioned thereabout.

37. The apparatus of claim 28 wherein said pairs of said interconnection electrodes in electrically conductive contact with a corresponding one of said bit structures are on substantially opposite sides thereof near or at substantially opposite edges of a said relative orientation maintenance intermediate layer major surface.

38. The apparatus of claim 30 wherein said bit structure having a said transistor in said plurality of transistors electrically coupled thereto has said coupling provided at least in part by one of said pair of said interconnection electrodes in electrically conductive contact therewith.

39. The apparatus of claim 31 wherein said bit structure having a said electronic circuit component electrically coupled thereto has said coupling provided at least in part by one of said pair of said interconnection electrodes in electrically conductive contact therewith.

40. A ferromagnetic thin-film based digital memory, said memory comprising:

a plurality of bit structures electrically interconnected with information storage and retrieval circuitry, said bit structures comprising;

a relative orientation maintenance intermediate layer having two major surfaces on opposite sides thereof;

a pair of memory films of an anisotropic ferromagnetic material each on a corresponding one of said relative orientation maintenance intermediate layer major surfaces, said relative orientation maintenance intermediate layer being of a material and a selected thickness so as to maintain magnetizations of said memory films oriented in substantially opposite directions, said pair of memory films having sufficiently similar magnetic moments so as to substantially maintain magnetization orientations thereof despite magnetic fields occurring thereabout due to changes of magnetizations orientations of those said pairs of memory films in other said bit structures in said plurality thereof under direction of said information storage and retrieval circuitry;

a nonmagnetic intermediate layer of a nonmagnetic material on one of said pair of memory films and across that said memory film from one of said relative orientation maintenance intermediate layer major surfaces with said nonmagnetic intermediate layer having a major surface on a side thereof opposite said pair of memory films; and

a magnetization reference layer on said major surface of said nonmagnetic intermediate layer having a substantially fixed magnetization direction;

interconnection electrodes having at least pairs thereof each in electrically conductive contact with a corresponding one of said bit structures with members in a said interconnection electrode pair contacting a corresponding said bit structure being spaced apart from one another such that at least one said member of a said interconnection electrode pair is near or at an edge of a said relative orientation maintenance intermediate layer major surface; and

a plurality of transistors electrically interconnected in said information storage and retrieval circuitry so that a said bit structure has a transistor in said plurality of transistors electrically coupled thereto at least in part by a member in that said interconnection electrode pair contacting that said bit structure so that said transistor selectively substantially prevents current in at least one direction through that said member and said bit structure.

41. The apparatus of claim 40 wherein said bit structures are provided on a substrate and said substrate further comprises a monolithic integrated circuit structure containing said plurality of transistors including said transistors electrically coupled to said bit structures.

42. The apparatus of claim 40 wherein said other member in that said electrode interconnection pair contacting a said bit structure is also near or at an edge of a said relative orientation maintenance intermediate layer major surface.

43. The apparatus of claim 42 wherein said other member in that said interconnection electrode pair contacting a said bit structure is electrically connected to another transistor in said plurality of transistors.

44. The apparatus of claim 40 wherein said other member in that said electrode interconnection pair contacting a said bit structure is at said magnetization reference layer.

45. The apparatus of claim 44 wherein said other member in that said interconnection electrode pair contacting a said bit structure is electrically connected to another transistor in said plurality of transistors.

46. The apparatus of claim 40 wherein said other member in that said interconnection electrode pair contacting a said bit structure is also near or at an edge of a said relative orientation maintenance intermediate layer major surface, and a further electrode is in electrical contact with that said bit structure at said magnetization reference layer.

47. The apparatus of claim 46 wherein at least one of said other member in that said interconnection electrode pair contacting a said bit structure and said further electrode is electrically connected to another transistor in said plurality of transistors.

48. The apparatus of claim 40 wherein at least said relative orientation maintenance intermediate layer and said pair of memory films of a said bit structure have a length extending from said member in that said electrode interconnection pair contacting a said bit structure near or at an edge of a said relative orientation maintenance intermediate layer major surface and a width substantially perpendicular thereto that is smaller in extent than said length, said width being less than about two curling lengths of said separate films from edges thereof substantially perpendicular to said width.

49. The apparatus of claim 40 wherein said nonmagnetic intermediate layer in a said bit structure is an electrical conductor.

50. The apparatus of claim 49 wherein said bit structures are provided on a substrate and said substrate further comprises a monolithic integrated circuit structure containing said plurality of transistors including said transistors electrically coupled to said bit structures.

51. The apparatus of claim 49 wherein said other member in that said electrode interconnection pair contacting a said bit structure is also near or at an edge of a said relative orientation maintenance intermediate layer major surface.

52. The apparatus of claim 51 wherein said other member in that said interconnection electrode pair contacting a said bit structure is electrically connected to another transistor in said plurality of transistors.

53. The apparatus of claim 49 wherein said other member in that said electrode interconnection pair contacting a said bit structure is at said magnetization reference layer.

54. The apparatus of claim 53 wherein said other member in that said interconnection electrode pair contacting a said bit structure is electrically connected to another transistor in said plurality of transistors.

55. The apparatus of claim 49 wherein said other member in that said interconnection electrode pair contacting a said bit structure is also near or at an edge of a said relative orientation maintenance intermediate layer major surface, and a further electrode is in electrical contact with that said bit structure at said magnetization reference layer.

56. The apparatus of claim 55 wherein at least one of said other member in that said interconnection electrode pair contacting a said bit structure and said further electrode is electrically connected to another transistor in said plurality of transistors.

57. The apparatus of claim 40 wherein said nonmagnetic intermediate layer in a said bit structure is an electrical insulator.

58. The apparatus of claim 57 wherein said bit structures are provided on a substrate and said substrate further comprises a monolithic integrated circuit structure containing said plurality of transistors including said transistors electrically coupled to said bit structures.

59. The apparatus of claim 57 wherein said other member in that said electrode interconnection pair contacting a said bit structure is also near or at an edge of a said relative orientation maintenance intermediate layer major surface.

60. The apparatus of claim 59 wherein said other member in that said interconnection electrode pair contacting a said bit structure is electrically connected to another transistor in said plurality of transistors.

61. The apparatus of claim 57 wherein said other member in that said electrode interconnection pair contacting a said bit structure is at said magnetization reference layer.

62. The apparatus of claim 61 wherein said other member in that said interconnection electrode pair contacting a said bit structure is electrically connected to another transistor in said plurality of transistors.

63. The apparatus of claim 57 wherein said other member in that said interconnection electrode pair contacting a said bit structure is also near or at an edge of a said relative orientation maintenance intermediate layer major surface, and a further electrode is in electrical contact with that said bit structure at said magnetization reference layer.

64. The apparatus of claim 63 wherein at least one of said other member in that said interconnection electrode pair contacting a said bit structure and said further electrode is electrically connected to another transistor in said plurality of transistors.

65. The apparatus of claim 40 wherein said magnetization reference layer in a said bit structure comprises an antiferromagnetic layer positioned at a major surface of a first reference ferromagnetic thin-film layer.

66. The apparatus of claim 65 wherein said magnetization reference layer further comprises a second reference ferromagnetic thin-film layer separated from said first reference ferromagnetic thin-film layer by an antiparallel magnetization directing layer forcing magnetizations of said first and second reference ferromagnetic thin-film layers to be oppositely directed.

67. The apparatus of claim 65 further comprising a plurality of electrical current conductors each positioned across an insulating layer from a corresponding said bit structure.

68. The apparatus of claim 67 wherein said plurality of bit structures are each supported on a substrate and separated from one another by spacer material therebetween, and wherein a magnetic material layer in said magnetization reference layer has a characteristic magnetic property that is maintained below a critical temperature above which such magnetic property is not maintained, said bit structures each having a first interconnection structure providing electrical contact thereto positioned against at least one side thereof, and said plurality of electrical conductors each exhibits sufficient electrical resistance where across from a selected said corresponding bit structure for a sufficient electrical current therethrough to cause substantial heating of said selected corresponding bit structure to raise temperatures thereof to have said magnetic material layer therein approach said critical temperature thereof while being substantially above temperatures of at least an adjacent said bit structure because of sufficient extents of, and smallness of thermal conductivities of, said first interconnection structure positioned against said selected corresponding bit structure and of those portions of said substrate and said spacer material positioned thereabout.