Semiconductor device

• US 6,777,756 B2
• Filed: 03/22/2002
• Issued: 08/17/2004
• Est. Priority Date: 03/26/2001
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohguro, Tatsuya
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US10/102,631
• Publication Number:
  US 20020137298A1
• Time in Patent Office: 879 Days
• Field of Search: 257/331, 257/365, 257/506, 257/510, 257/366, 257/387, 257/388, 257/401, 257/412, 257/413, 438/284, 438/365
• US Class Current: 257/365
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out

Abstract

An aspect the present invention is to provide a semiconductor device including at least one MISFET structure having an element isolation region formed on a surface portion of a semiconductor substrate to have a closed region, an element region formed on the surface region of the semiconductor substrate to surround the element isolation region, a gate insulating film formed to cover at least the surface of the element region, a contact region formed on the element isolation region, and at least four gate electrodes connected to the contact region and formed on the surface of the element region via the gate insulating film to extend to at least outside the element region.

Claims

1. A semiconductor device including at least one MISFET structure, said MISFET structure comprising:

an element isolation region formed on a surface portion of a semiconductor substrate to have a closed region;

an element region formed on the surface region of the semiconductor substrate to surround said element isolation region;

a gate insulating film formed to cover at least a surface of said element region;

a contact region formed on said element isolation region; and

at least four gate electrodes connected to said contact region and formed on the surface of said element region via said gate insulating film to extend to at least outside said element region,

wherein in said element region, regions partitioned by said gate electrodes are alternately allocated to source regions and drain regions, and an area of at least one of said drain regions is different from that of at least one of said source regions.

2. The device according to claim 1, wherein

said device comprises a plurality of MISFET structures, and

gate electrodes of said MISFET structures are electrically connected to each other.

3. The device according to claim 1, wherein at least one of said drain regions has an area smaller than that of at least one of said source regions.

4. The device according to claim 1, wherein a total area of said drain regions is smaller than a total area of said source regions.

5. The device according to claim 3, wherein said device comprises a plurality of MISFET structures, and

gate electrodes of said MISFET structures are electrically connected to each other.

6. The device according to claim 5, wherein adjacent source regions between said plurality of MISFET structures, and adjacent drain regions between said plurality of MISFET structures are connected.

7. The device according to claim 5, wherein at least one of said drain regions has an area smaller than that of at least one of said source regions.

8. The device according to claim 5, wherein a total area of said drain regions is smaller than a total area of said source regions.

9. The device according to claim 8, wherein adjacent source regions between said plurality of MISFET structures are connected, and adjacent drain regions between said plurality of MISFET structures are connected.

10. The device according to claim 1, wherein an outer peripheral shape of said element region in each MISFET structure is rectangular when the number of gate electrodes is four, hexagonal when the number of gate electrode is six, and octagonal when the number of gate electrodes is eight.