Drive circuit to be used in active matrix type light-emitting element array

• US 6,777,888 B2
• Filed: 09/20/2002
• Issued: 08/17/2004
• Est. Priority Date: 03/21/2001
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Kondo, Shigeki
• Primary Examiner(s): Wong, Don
• Assistant Examiner(s): Alemu, Ephrem
• Application Number:
  US10/247,303
• Publication Number:
  US 20030016190A1
• Time in Patent Office: 697 Days
• Field of Search: 315/169.1, 315/169.3, 315/169.4, 345/76-78, 345/80, 345/82, 345/84, 345/92, 345/55
• US Class Current: 315/169.3
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0251 Precharge or discharge of pixel before applying new pixel voltage
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2320/02 Improving the quality of display appearance
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/0252 Improving the response speed
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element

Abstract

In a drive circuit to be used for a light-emitting panel formed by a light-emitting element array having a matrix type configuration, wherein a plurality of thin film transistors are arranged for each pixel of the light-emitting element array, a circuit for canceling the offset voltage of a drive transistor is provided by arranging a memory capacitance at the input side of the light-emitting element to instantly accumulate the offset voltage of the drive transistor so as to offset the phenomenon of the voltage fall that is equal to the offset voltage when an image signal s applied at the next timing. With this arrangement, variances in the characteristic of the drive transistors can be cancelled to lessen the variances in the brightness of the light-emitting elements and improve the high speed response of the light-emitting elements.

Claims

1. A drive circuit to be used in an active matrix type light-emitting element array comprising scan lines and signal lines arranged on a substrate to form a matrix and unit pixels formed near the respective crossings of the scan lines and the signal lines, each unit pixel including a light-emitting element and a plurality of thin film transistors each having a source electrode, a gate electrode and a drain electrode, said drive circuit comprising:

a first circuit section including a first thin film transistor (M1) having a gate electrode connected to a scan line, a source electrode connected to a signal line and a drain electrode;

a second circuit section including a light-emitting element having an electrode connected to a first power source and a second thin film transistor (M2) having a gate electrode, a source electrode connected to a second power source and a drain electrode connected to another electrode of the light-emitting element, hence said light-emitting element being connected in series to said second thin film transistor; and

a third circuit section including a third thin film transistor (M3) having a gate electrode connected to a control signal line, a source electrode connected to a reference power source and a drain electrode connected to the gate electrode of said second thin film transistor;

the drain electrode of said first thin film transistor being connected to the gate electrode of said second thin film transistor by way of a memory capacitance (C1);

the drain electrodes of said first and second thin film transistors being commonly connected.

2. A circuit according to claim 1, wherein

the voltage of said reference power source is higher than the threshold voltage of said second thin film transistor.

3. A circuit according to claim 1, wherein

the voltage of said reference power source is lower than the light emission threshold voltage of said light-emitting element.

4. A circuit according to claim 1, further comprising:

a fourth circuit section including a fourth thin film transistor (M4) having a source electrode connected to a reset voltage and a drain electrode connected commonly to the input terminal of said light-emitting element.

5. A circuit according to claim 4, wherein

the voltage of said reference power source is higher than the threshold voltage of said second thin film transistor.

6. A circuit according to claim 4, wherein

the reset voltage is lower than the light emission threshold voltage of said light-emitting element.

7. A circuit according to claim 4, wherein

the reset voltage is equal to the ground potential.

8. A circuit according to claim 4, wherein

said circuit is provided with a function of forcibly terminating the light-emitting state of said light-emitting element by turning on said fourth transistor.

9. An active matrix type display device comprising a plurality of pixel sections arranged in the form of a matrix, said pixel sections respectively having drive circuits and light-emitting elements as defined in claim 1.