High-performance network processor

• US 6,778,534 B1
• Filed: 06/30/2000
• Issued: 08/17/2004
• Est. Priority Date: 06/30/2000
• Status: Expired due to Term

• Current Assignee: Mellanox Technologies Limited (NVIDIA Corporation)
• Original Assignee: Ezchip Technologies Ltd. (NVIDIA Corporation)
• Inventors: Gabbay, Itzchak, Rivkin, Dennis, Horovitz, Ziv, Frumkin, Gllad, Shefi, Yohay, Rachamim, Shifra, Kaplan, Sharon, Tal, Alex
• Primary Examiner(s): Ton, Dang
• Assistant Examiner(s): Phan, Tri H.
• Application Number:
  US09/609,221
• Time in Patent Office: 1,509 Days
• Field of Search: 370/349, 370/389, 370/392, 370/471, 370/474, 709/201, 709/236, 709/238, 709/249, 709/228, 709/242, 707/1, 707/3, 707/7, 716/2, 716/4, 716/12, 716/13, 716/14
• US Class Current: 370/392
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof

Abstract

A high-speed system for processing a packet and routing the packet to a packet destination port, the system comprising: (a) a memory block for storing tabulated entries, (b) a parsing subsystem containing at least one microcode machine for parsing the packet, thereby obtaining at least one search key, (c) a searching subsystem containing at least one microcode machine for searching for a match between said at least one search key and said tabulated entries, (d) a resolution subsystem containing at least one microcode machine for resolving the packet destination port, and (e) a modification subsystem containing at least one microcode machine for making requisite modifications to the packet; wherein at least one of said microcode machines is a customized microcode machine.

Claims

1. A high-speed system for processing a packet and routing the packet to a requisite packet destination port, the system comprising:

a single chip having;

(a) a memory block, embedded within said single chip, for storing tabulated entries, and

(b) a plurality of microcode machines, disposed within said single chip, interacting with said memory block, accessing said tabulated entries, processing the packet, and routing the packet,

wherein said plurality of microcode machines include a hardware-customized microcode machine.

2. The system of claim 1, said hardware-customized microcode machine being designed to achieve a specific well-defined task.

3. The system of claim 2, wherein said hardware-customized microcode machine is a CISC processor.

4. The system of claim 2, wherein said plurality of microcode machines includes a plurality of hardware-customized microcode machines.

5. The system of claim 4, wherein each of said hardware-customized microcode machines is designed for performing a different, specific, well-defined task.

6. The system of claim 4, wherein said plurality of hardware-customized microcode machines is designed for performing a parsing function and a searching function, and wherein at least one hardware-customized microcode machine of said plurality is designed for performing a single function of said functions.

7. The system of claim 6, wherein said single function is said parsing function.

8. The system of claim 6, wherein said single function is said searching function.

9. The system of claim 4, wherein said plurality of hardware-customized microcode machines is designed for performing a resolution function in which a destination port of the packet is resolved.

10. The system of claim 4, wherein said plurality of hardware-customized microcode machines is designed for performing a modification function in which the packet is modified.

11. The system of claim 4, wherein said plurality of hardware-customized microcode machines is designed for performing at least two functions selected from the group consisting of:

a parsing function, a searching function, a resolution function in which a destination port of the packet is resolved, and a modification function in which the packet is modified, and wherein at least one hardware-customized microcode machine of said plurality is designed for performing a single function of said functions.

12. The system of claim 11, wherein said single function of said functions is said parsing function.

13. The system of claim 11, wherein said single function of said functions is said searching function.

14. The system of claim of 11, wherein said single function of said functions is said resolution function.

15. The system of claim 11, wherein said single function of said functions is said modification function.

16. The system of claim 4, wherein said plurality of hardware-customized microcode machines is configured for super-scalar architecture.

17. The system of claim 1, wherein said hardware-customized microcode machine has a customized instruction set.

18. The system of claim 4, wherein said plurality of hardware-customized microcode machines have a customized data path.

19. A high-speed system for processing a packet and routing the packet to the requisite packet destination port, the system comprising:

(a) a memory block for storing tabulated entries, and

(b) a plurality of microcode machines, for interacting with said memory block, accessing said tabulated entries, processing the packet, and routing the packet,

wherein at least one of said plurality of microcode machines is a hardware-customized microcode machine, and

wherein said plurality of microcode machines is designed for performing at least two functions selected from the group consisting of;

a parsing function, a searching function, a resolution function in which a destination port of the packet is resolved, and a modification function in which the packet is modified, and wherein at least said hardware-customized microcode machine is designed for performing a single function of said functions.

20. The system of claim 19, wherein said single function of said functions is said parsing function.

21. The system of claim 19, wherein said single function of said functions is said searching function.

22. The system of claim 19, wherein said single function of said functions is said resolution function.

23. The system of claims 19, wherein said single function of said functions is said modification function.

24. The system of claim 19, wherein said plurality of microcode machines is a plurality of hardware-customized microcode machines.

25. The system of claim of 24, wherein said plurality of hardware-customized microcode machines is configured for super-scalar architecture.

26. The system of claim 24, wherein said plurality of hardware-customized microcode machines is disposed in a single chip.

27. The system of claim 26, wherein each of said hardware-customized microcode machines is designed for performing a different, specific, well-defined task.