Processing semiconductor devices having some defective input-output pins

• US 6,778,933 B2
• Filed: 12/10/2002
• Issued: 08/17/2004
• Est. Priority Date: 12/07/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Prak, Sovandy, Charlton, David
• Primary Examiner(s): Wachsman, Hal D
• Application Number:
  US10/315,594
• Publication Number:
  US 20030125896A1
• Time in Patent Office: 616 Days
• Field of Search: 702/117, 702/118, 702/33-35, 702/38, 702/40, 702/57-59, 702/64, 702/65, 702/81-84, 702/108, 702/119-123, 702/170, 702/172, 702/182-185, 702/FOR.170, 702/FOR.171, 702/FOR-103, 702/FOR-123, 702/FOR.131, 702/FOR.134, 702/FOR.135, 702/FOR.137, 702/FOR.138, 700/109, 700/110, 700/115-121, 365/201, 438/5, 438/7, 438/10-12, 438/14, 438/16-18, 382/141, 382/144-146, 382/147, 382/149, 209/571-574, 324/73.1, 324/764, 324/765, 324/555, 324/761, 324/158.1, 324/763, 324/515, 324/532, 324/755, 714/724, 714/718, 714/725
• US Class Current: 702/118
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/886 combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device

Abstract

Techniques to process semiconductor devices whose input-output (I/O) pins are only partially operative is able to accommodate substantially all possible combinations of operative I/O pin patterns. Semiconductor devices are tested to determine which I/O pins are operative. A code representing which I/O pins are operative is then associated with each tested device. The generated codes are used to selectively combine two or more semiconductor devices to form a component capable of providing the function of a single fully operational semiconductor device.

Claims

1. A method to process partially defective devices each having plural pins, comprising:

testing the devices to identify which pins are operational and which pins are inoperational;

storing a code indicating an operational status of the pins; and

prior to assembling the devices into a module, verifying the operational status of at least the pins indicated by the code as being operational.

2. The method of claim 1, wherein verifying the operational status comprises performing a second test of each device.

3. The method of claim 2, wherein performing the second test comprises performing at least one of a device speed test, pin-to-pin current test, current drain measurement, voltage-on low and high test, and noise immunity test.

4. The method of claim 3, wherein testing the devices to identify which pins are operational and which pins are inoperational comprises performing burn-in testing.

5. The method of claim 1, further comprising updating the code based on the verifying.

6. The method of claim 1, further comprising disabling one or more pins that are indicated by the code as being inoperational.

7. A method to process partially defective devices each having plural pins, comprising:

testing the devices to identify which pins are operational and which pins are inoperational;

storing a code indicating an operational status of the pins;

prior to assembling the devices into a module, verifying the operational status of at least the pins indicated by the code as being operational; and

storing an identifier of each of the devices, the identifier associated with the code.

8. The method of claim 7, wherein verifying the operational status uses the identifier and code of each device.

9. A program storage device, readable by a programmable control system, comprising instructions that when executed cause the programmable control system to:

test devices to identify which pins of the devices are operational and which pins are inoperational;

store a code indicating an operational status of the pins; and

verify the operational status of at least the pins of the devices indicated by the code as being operational prior to assembling the devices into a module.

10. The program storage device of claim 9, wherein the instructions when executed cause the programmable control system to verify the operational status by performing a second test.

11. The program storage device of claim 10, wherein performing the second test comprises performing at least one of a device speed test, pin-to-pin current test, current drain measurement, voltage-on low and high test, and noise immunity test.

12. The program storage device of claim 11, wherein testing the devices to identify which pins of the devices are operational and which pins are inoperational comprises performing burn-in testing.

13. The program storage device of claim 9, wherein the instructions when executed cause the programmable control system to update the code based on the verifying.

14. A test system comprising:

a first tester to test devices to identify which pins are operational and which pins are inoperational;

a storage to store a code indicating an operational status of the pins; and

a second tester to verify the operational status of at least the pins indicated by the code as being operational prior to assembling the devices into a module.

15. The test system of claim 14, wherein the second tester verifies the operational status by performing a second test.

16. The test system of claim 15, wherein the second test comprises at least one of a device speed test, pin-to-pin current test, current drain measurement, voltage-on low and high test, and noise immunity test.

17. The test system of claim 16, wherein the first tester comprises a burn-in tester.