Enhanced time-shared data correlator architecture and method

• US 6,779,009 B1
• Filed: 05/21/2001
• Issued: 08/17/2004
• Est. Priority Date: 05/21/2001
• Status: Expired due to Term

• Current Assignee: Rockwell Collins, Inc. (Rtx Corporation)
• Original Assignee: Rockwell Collins, Inc. (Rtx Corporation)
• Inventors: Zuber, Eric O.
• Primary Examiner(s): Ngo, Chuong Dinh
• Application Number:
  US09/862,129
• Time in Patent Office: 1,184 Days
• Field of Search: 708/300, 708/301, 708/316, 708/315, 708/319, 708/420, 708/421, 708/422, 708/423, 708/424, 708/425, 708/426
• US Class Current: 708/422
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00

Abstract

An enhanced architecture time-shared data correlator for performing a predetermined number of correlation processes. A data shift register receives input data and loads the input data. A reference shift register receives reference data and loads and circulates the reference data. A pulse correlator connected to the shift register and the reference shift register correlates the input data with the corresponding reference data and provides a pulse correlator output. An accumulator connected to the pulse correlator receives and adds the pulse correlator outputs from the correlation processes to produce a correlator output corresponding to the predetermined number of correlation processes.

Claims

1. An enhanced architecture time-shared data correlator for performing a predetermined number of correlation processes comprising:

a data shift register having a predetermined number of input lines for receiving a predetermined number of input data code words of length N at an input data rate and loading the input data code words at a multiple of the input data rate;

a reference shift register for receiving a predetermined number of reference data code words of length N and loading the reference data code words at the multiple of the input data rate;

a pulse correlator of length N connected to the data shift register and the reference shift register for correlating each of the predetermined number of input data code word with its corresponding reference data code word at the multiple of the input data rate to provide a predetermined number of pulse correlator outputs; and

an accumulator connected to the pulse correlator for receiving and adding the predetermined number of pulse correlator outputs in accordance with a load/add control signal at a multiple of the input data rate to provide a correlator output.

2. The enhanced architecture time-shared data correlator of claim 1 wherein the predetermined number of correlation processes equals the predetermined number of input data code words.

3. The enhanced architecture time-shared data correlator of claim 1 wherein the predetermined number of correlation processes equals the multiple of the input data rate.

4. The enhanced architecture time-shared data correlator of claim 1 wherein the predetermined number of correlation processes equals to the predetermined number of reference data code words.

5. The enhanced architecture time-shared data correlator of claim 1 wherein the data shift register further comprises a shift register of length 2N times the predetermined number of correlation processes.

6. The enhanced architecture time-shared data correlator of claim 1 wherein the reference shift register further comprises N individual shift registers of a length equal to the predetermined number of correlation processes.

7. A method of performing a predetermined number of correlation processes in an enhanced architecture time-shared data correlator comprising the steps of:

receiving a predetermined number of input data code words at an input data rate at a data shift register;

loading into the data shift register the predetermined number of input data code words at a multiple of the input data rate;

loading into a reference shift register a predetermined number of reference data code words;

circulating the reference data code words in the reference shift register at the multiple of the input data rate;

correlating each of the predetermined number of input data code words with its corresponding reference data code word in a pulse correlator connected to the data shift register and the reference shift register at a multiple of the input data rate;

providing a pulse correlator output from the pulse correlator for each of the correlation steps;

receiving at an accumulator connected to the pulse correlator the pulse correlator outputs;

adding the pulse correlator outputs in the accumulator; and

providing a correlator output that is a sum of the pulse correlator outputs for the correlation of each of the input data code words and its corresponding reference code word.

8. The method of performing the predetermined number of correlation processes in an enhanced architecture time-shared data correlator of claim 7 wherein the predetermined number of correlation processes corresponds to the predetermined number of input data code words.

9. The method of performing the predetermined number of correlation processes in an enhanced architecture time-shared data correlator of claim 7 wherein the predetermined number of correlation processes equals the multiple of the input data rate.

10. The method of performing the predetermined number of correlation processes in an enhanced architecture time-shared data correlator of claim 7 wherein the predetermined number of correlation processes equals the predetermined number of reference data code words.

11. An enhanced architecture time-shared data correlator for performing a predetermined number of correlation processes comprising:

a data shift register for receiving and loading a predetermined number of input data;

a reference shift register for sequentially receiving reference data and loading and circulating the reference data;

a pulse correlator connected to the data shift register and the reference shift register for correlating the input data with corresponding reference data and providing a pulse correlator output; and

an accumulator connected to the pulse correlator for receiving and adding the pulse correlator outputs to provide a correlator output.

12. The enhanced architecture time-shared data correlator of claim 11 wherein the data shift register comprises a predetermined number of input lines for receiving input data code words of length N at an input data rate and for loading the input data code words at a multiple of the input data rate.

13. The enhanced architecture time-shared data correlator of claim 12 wherein the data shift register further comprises a predetermined number of shift register stages for loading and circulating the input data at the multiple of the input data rate.

14. The enhanced architecture time-shared data correlator of claim 12 wherein the reference shift register further comprises N individual shift registers of a length equal to the predetermined number of correlation processes said N individual shift registers for receiving reference data and loading and circulating the reference data at a multiple of the input data rate.