Contactless integrated circuit comprising a wired logic anticollision circuit

• US 6,779,091 B2
• Filed: 04/03/2002
• Issued: 08/17/2004
• Est. Priority Date: 04/04/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Moreaux, Christophe, Kari, Ahmed
• Primary Examiner(s): Moazzami, Nasser
• Assistant Examiner(s): Farrokh, Hashem
• Application Number:
  US10/115,869
• Publication Number:
  US 20020180487A1
• Time in Patent Office: 867 Days
• Field of Search: 235/380, 235/382, 235/492, 342/42, 342/44, 342/51, 370/205, 370/213, 365/183, 365/189, 365/189.12, 365/221, 365/230, 711/101-105, 711/109, 711/154, 711/164
• US Class Current: 711/154
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/10019 resolving collision on the communication channels between simultaneously or concurrently interrogated record carriers. collision between the communication channels used by wireless communication devices, where the solution is not particularly adapted for RFIDs or the like, H04W74/08
• CPC Class Codes: G06K 7/10346 the antenna being of the far field type, e.g. HF types or dipoles
• CPC Class Codes: G07C 9/28 the pass enabling tracking or indicating presence

Abstract

An integrated circuit having an identification code of M bits includes a communication interface circuit for receiving a selective identification request and a selection code, and a processing circuit connected thereto. The processing circuit includes a logic comparator having a first input for receiving the selection code and a second input for receiving the identification code, and an output for delivering an equal signal if the selection and identification codes are equal. A shift register has an output coupled to the first input of the logic comparator. A serial memory stores the identification code, and has a serial output coupled to the second input of the logic comparator and to a serial input of the shift register. A controller is connected to the shift register and to the serial memory for loading the selection code into the shift register, and for applying M shift pulses to the shift register and M read pulses to the serial memory. An inhibiting circuit inhibits the logic comparator when N shift and read pulses have been applied to the shift register and to the serial memory.

Claims

1. An integrated circuit having an identification code of M bits, and comprising:

a communication interface circuit for receiving a selective identification request and a selection code; and

a processing circuit connected to said communication interface circuit for processing the selective identification request and the selection code, said processing circuit comprising;

a logic comparator having a first input for receiving the selection code and a second input for receiving the identification code, and an output for delivering an equal signal if the selection and identification codes are equal,

a shift register having a serial output coupled to the first input of said logic comparator for providing the selection code thereto,

a serial memory for storing the identification code and having a serial output coupled to the second input of said logic comparator and to a serial input of said shift register,

a controller connected to said shift register and to said serial memory for loading the selection code into said shift register, and for applying M shift pulses to said shift register and M read pulses to said serial memory,

an inhibiting circuit connected to said shift register, to said controller and to said logic comparator for inhibiting said logic comparator when N shift and read pulses have been applied to said shift register and to said serial memory, and

a data delivery circuit for delivering to said communication interface circuit data in said shift register when said logic comparator delivers the equal signal.

2. An integrated circuit according to claim 1, wherein said inhibiting circuit comprises a first counting circuit for counting the N shift and read pulses in synchronization with one another, and for delivering an inhibit signal to said logic comparator when the N shift and read pulses have been counted.

3. An integrated circuit according to claim 2, wherein said first counting circuit comprises:

a down-counter for receiving a signal from said controller corresponding to the number N; and

a logic circuit connected to said down-counter for delivering the inhibit signal when said down-counter reaches zero.

4. An integrated circuit according to claim 1, wherein said inhibiting circuit inhibits said logic comparator when said logic comparator delivers an unequal signal if the selection and identification codes are not equal.

5. An integrated circuit according to claim 2, wherein said inhibiting circuit inhibits said first counting circuit when said logic comparator delivers an unequal signal if the selection and identification codes are not equal.

6. An integrated circuit according to claim 1, wherein said logic comparator comprises a plurality of synchronous latches driven by a synchronization signal synchronized with the shift and read pulses.

7. An integrated circuit according to claim 6, wherein said inhibiting circuit comprises a logic gate for blocking the synchronization signal to said plurality of synchronous latches.

8. An integrated circuit according to claim 1, wherein said data delivery circuit delivers an authorization signal to said controller when said logic comparator delivers the equal signal, and comprises a logic circuit for preventing the delivery of the authorization signal when said logic comparator delivers an unequal signal if the selection and identification codes are not equal;

and wherein said controller couples the serial output of said shift register to said communication interface circuit when the authorization signal is delivered.

9. An integrated circuit according to claim 8, wherein said data delivery circuit counts a number P and delivers the authorization signal when the number P is counted;

and wherein said controller applies a counting signal to said data delivery circuit at each reception by said communication interface circuit of a response request to the selective identification request.

10. An integrated circuit according to claim 9, wherein said data delivery circuit comprises:

a down-counter;

a first logic circuit for loading the number P into said down-counter; and

a second logic circuit for delivering the authorization signal when said down-counter reaches zero.

11. An integrated circuit according to claim 10, wherein said first logic circuit starts the loading of the number P after application of the N shift pulses to said shift register and the N read pulses to said serial memory if said logic comparator does not deliver the unequal signal.

12. An integrated circuit according to claim 11 wherein said first logic circuit starts the loading of the number P into said down-counter after a bit by bit loading of L bits of the identification code after the N read pulses.

13. An integrated circuit according to claim 12 wherein said data delivery circuit comprises a counter for counting the L bits in one bit loading cycles;

and wherein said first logic circuit inhibits loading of said down-counter when the number L is reached.

14. An integrated circuit according to claim 1, wherein said shift register includes a parallel input for receiving the selection code from said controller.

15. An integrated circuit according to claim 1, wherein said shift register comprises:

a demultiplexer circuit;

a plurality of sub-registers connected in parallel, each sub-register having a serial input connected to said demultiplexer circuit, and a serial output; and

a multiplexer circuit connected to a serial output of each sub-register.

16. An integrated circuit according to claim 1, wherein said communication interface circuit comprises a contactless communication interface operating via inductive coupling.

17. An integrated circuit according to claim 1, wherein the selective identification request is in accordance with an ISO/IEC/FCD 15693-3 standard.

18. A contactless chip card comprising:

a contactless communication interface circuit operating via inductive coupling for receiving a selective identification request and a selection code;

a logic comparator having a first input for receiving the selection code and a second input for receiving an identification code having N bits assigned to the contactless chipcard, and an output for delivering an equal signal if the selection and identification codes are equal;

a shift register having a serial output coupled to the first input of said logic comparator for providing the selection code thereto;

a serial memory for storing the identification code and having a serial output coupled to the second input of said logic comparator and to a serial input of said shift register;

a controller connected to said contactless communication interface circuit, to said shift register and to said serial memory for loading the selection code into said shift register, and for applying M shift pulses to said shift register and N read pulses to said serial memory; and

an inhibiting circuit connected to said shift register, to said controller and to said logic comparator for inhibiting said logic comparator when N shift and read pulses have been applied to said shift register and to said serial memory.

19. A contactless chip card according to claim 18, further comprising a data delivery circuit for delivering to said contactless communication interface circuit data in said shift register when said logic comparator delivers the equal signal.

20. A contactless chip card according to claim 18, wherein said inhibiting circuit comprises a first counting circuit for counting the N shift and read pulses in synchronization with one another, and for delivering an inhibit signal to said logic comparator when the N shift and read pulses have been counted.

21. A contactless chip card according to claim 20, wherein said first counting circuit comprises:

a down-counter for receiving a signal from said controller corresponding to the number N; and

a logic circuit connected to said down-counter for delivering the inhibit signal when said down-counter reaches zero.

22. A contactless chip card according to claim 18, wherein said inhibiting circuit inhibits said logic comparator when said logic comparator delivers an unequal signal if the selection and identification codes are not equal.

23. A contactless chip card according to claim 18, wherein said data delivery circuit delivers an authorization signal to said controller when said logic comparator delivers the equal signal, and comprises a logic circuit for preventing the delivery of the authorization signal when said logic comparator delivers an unequal signal if the selection and identification codes are not equal;

and wherein said controller couples the serial output of said shift register to said communication interface circuit when the authorization signal is delivered.

24. A contactless chip card according to claim 18, wherein said shift register comprises:

a demultiplexer circuit;

a plurality of sub-registers connected in parallel, each sub-register having a serial input connected to said demultiplexer circuit, and a serial output; and

a multiplexer circuit connected to a serial output of each sub-register.

25. A method for processing a selective identification request and a selection code in an integrated circuit having an identification code of M bits, the integrated circuit comprising a communication interface circuit for receiving the selective identification request and the selection code, a logic comparator having a first input for receiving the selection code and a second input for receiving the identification code, a shift register having a serial output coupled to the first input of the logic comparator, and a serial memory having a serial output coupled to the second input of the logic comparator and to a serial input of the shift register, the method comprising:

storing the identification code in the serial memory;

loading the selection code into the shift register;

applying M shift pulses to the shift register and M read pulses to the serial memory;

inhibiting the logic comparator when N shift and read pulses have been applied to the shift register and to the serial memory;

delivering an equal signal from an output of the logic comparator if the selection and identification codes are equal; and

delivering to the communication interface circuit data in the shift register when the logic comparator delivers the equal signal.

26. A method according to claim 25, wherein inhibiting the logic circuit is performed using an inhibiting circuit connected to the shift register and to the logic comparator;

and further comprising;

counting the N shift and read pulses in synchronization with one another; and

delivering an inhibit signal to the logic comparator when the N shift and read pulses have been counted.

27. A method according to claim 25, further comprising inhibiting the logic comparator when the logic comparator delivers an unequal signal if the selection and identification codes are not equal.

28. A method according to claim 25, further comprising delivering an authorization signal to a controller when the logic comparator delivers the equal signal;

wherein the controller is connected to the shift register, the serial memory and to the communication interface circuit; and

further comprising;

using the controller for preventing the delivery of the authorization signal when the logic comparator delivers an unequal signal if the selection and identification codes are not equal; and

using the controller for coupling the serial output of the shift register to the communication interface circuit when the authorization signal is delivered.

29. A method according to claim 28, wherein delivering to the communication interface circuit data in the shift register is performed using a data delivery circuit that counts a number P and delivers the authorization signal when the number P is counted;

and wherein the controller applies a counting signal to the data delivery circuit at each reception by the communication interface circuit of a response request to the selective identification request.

30. A method according to claim 29, wherein the data delivery circuit comprises:

a down-counter;

a first logic circuit for loading the number P into the down-counter; and

a second logic circuit for delivering the authorization signal when said down-counter reaches zero.

31. A method according to claim 30, wherein the first logic circuit starts the loading of the number P after application of the N shift pulses to the shift register and the N read pulses to the serial memory if the logic comparator does not deliver the unequal signal.

32. A method according to claim 31, wherein the first logic circuit starts the loading of the number P into the down-counter after a bit by bit loading of L bits of the identification code after the N read pulses.

33. A method according to claim 25, wherein the shift register comprises:

a demultiplexer circuit;

a plurality of sub-registers connected in parallel, each sub-register having a serial input connected to the demultiplexer circuit, and a serial output; and

a multiplexer circuit connected to a serial output of each sub-register.

34. A method according to claim 25, wherein the selective identification request is in accordance with an ISO/IEC/FCD 15693-3 standard.