Fault-tolerant data transfer

• US 6,779,128 B1
• Filed: 02/18/2000
• Issued: 08/17/2004
• Est. Priority Date: 02/18/2000
• Status: Expired due to Fees

• Current Assignee: Schneider Electric Systems USA, Inc. (Schneider Electric SE)
• Original Assignee: Invensys Systems Incorporated (Invensys PLC)
• Inventors: Gale, Alan, Cummings, Gene, Bourdin, Christain
• Primary Examiner(s): Beausoliel, Robert
• Assistant Examiner(s): PUENTE, EMERSON C
• Application Number:
  US09/507,326
• Time in Patent Office: 1,642 Days
• Field of Search: 714/42, 714/43, 714/52, 714/718, 714/719, 714/6, 714/7, 714/8
• US Class Current: 714/6.12
• CPC Class Codes: G05B 19/00 Programme-control systems

Abstract

A control system has a first module that includes a memory and diagnostic logic. The diagnostic logic periodically tests at least selected locations in the memory and, in connection with such testing, reads data from those locations and writes that data back to the locations. A second module is coupled to the first module such that the written back data is transferred to the second module, as well as to the memory of the first. Mapping or other conversion logic can translate addresses or other data identifiers, as necessary, to insure that the transferred data is properly identified upon its receipt by the second module.

Claims

1. A control system comprising

a first module and a second module, each forming at least part of any of a workstation, field controller, field device, smart field device, or other functionality for any of industrial, manufacturing, service, environmental, or process control,

the first module comprising a first memory element that is normally coupled to a first bus and that stores data in accord with commands received over that bus,

the second module comprising a second memory element that is normally coupled to a second bus and that stores data in accord with commands received over that bus,

diagnostic logic, coupled to at least the first bus, that issues commands causing data in at least selected storage locations in the first memory element to be periodically re-written to those storage locations via the first bus,

switching logic coupled to the first and second modules, the switching logic transmitting to the second module at least selected data on the first bus,

wherein the witching logic has a memory update mode that selectively couples the second memory element to the first bus and decouples the second memory element from the second bus during a period in which the diagnostic logic is causing data in the selected storage locations in the first memory element to be re-written to those storage locations.

2. A control system according to claim 1, wherein the switching logic comprises any of a bus, network and other communications medium.

3. A control system according to claim 1, comprising logic that converts any of an address, symbolic name or other identifier associated with data transferred between the modules.

4. A control system according to claim 1, wherein the switching logic transfers any of bits, bytes, words, longwords, records, arrays, matrices, structs, objects, data structures or other items or portions of memory between the first module and the second module.

5. A control device, comprising:

a first memory element that is normally coupled to a first bus and that stores data in accord with commands received over that bus,

a second memory element that is normally coupled to a second bus and that stores data in accord with commands received over that bus,

a switching element that is coupled to the first and second memory elements and to the first and second buses, the switching element having a mode that temporarily couples the first memory element to the second bus, while decoupling the first memory element from the first bus, and

logic coupled to at least the second bus that issues commands causing data in at least selected storage locations in the second memory element to be re-written to those storage locations.

6. The control device of claim 5, wherein said logic issues commands causing data in at least selected storage locations in the second memory element to be periodically re-written to those storage locations.

7. The control device of any of claims 5 and 6, wherein the switching element couples the first memory element to the second bus for a period sufficient to ensure that substantially all of the selected storage locations in the second memory element are re-written.

8. The control device of claim 7, wherein the switching element comprises an FET switch.

9. The control device of claim 7, wherein the switching element comprises an FET switch array.

10. The control dice of claim 9, wherein each element of the FET switch array selectively couples conductors in the second bus to respective conductors of the first memory element.

11. A control device, comprising:

a first memory element that is normally coupled to a first bus and that stores data in accord with commands received over that bus,

a second memory element that is normally coupled to a second bus and that stores data in accord with commands received over that bus,

first memory test logic coupled to at least the second bus, the first memory test logic issuing commands causing data in at least selected storage locations in the second memory element to be periodically rewritten to those storage locations,

a first switching element having a memory update mode that selectively couples the first memory element to the second bus and decouples the first memory element from the first bus, during a period in which the first memory test logic is causing data in the selected storage locations in the second memory element to be re-written to those storage locations.

12. A control device according to claim 11, comprising

second memory test logic coupled to at least the first bus, the second memory test logic issuing commands causing data in at least selected storage locations in the first memory element to be periodically re-written to those storage locations,

a second switching element having a memory update mode that selectively couples the second memory element to the first bus and decouples the second memory element from the second bus, during a period in which the second memory test logic is causing data in the selected storage locations in the first memory element to be re-written to those storage locations.

13. A control device according to claim 12, wherein the first and second switching elements are not concurrently in their respective memory update modes.

14. The control device of claim 11, wherein at least one of the switching elements comprises an FET switch.

15. The control device of claim 11, wherein at least one of the switching elements comprises an FET switch array.

16. The control device of claim 15, wherein each element of the FET switch array couples conductors in the first and second buses to respective conductors of a respective one of the memory elements.

17. A control device, comprising:

a first module and a second module operating with at least loose coupling,

the first module comprising

a first processor that is coupled to a first bus,

a first memory element that stores data in accord with commands received over a bus to which it is coupled,

the first processor having a memory test mode wherein it issues issuing commands causing data in at least selected storage locations in the first memory element to be periodically re-written to those storage locations,

the second module comprising

a second processor that is coupled to a second memory element by a second bus,

a second memory element that stores data in accord with commands received over a bus to which it is coupled,

a switching element that is coupled to the first and second buses and the second memory element, the switching element having a conventional operation mode that couples the second bus to the second memory element, and that has a memory update mode that couples the first bus to the second memory element,

logic that changes the first switching element from the conventional operation mode to the memory update during a period in which the first processor is in the memory test mode.

19. The control device of any of claims 17 and 18, wherein at least one of the switching elements comprises an FET switch array.

20. The control device of claim 19, wherein each element of the FET switch array couples conductors in the first and second buses to respective conductors of a respective one of the memory elements.

18. A control device, comprising:

a first module and a second module operating with at least loose coupling,

the first module comprising

a first processor that is coupled to a first bus,

a first memory element that stores data in accord with commands received over a bus to which it is coupled,

the second module comprising

a second processor that is coupled to a second bus,

a second memory element that stores data in accord with commands received over a bus to which it is coupled,

the first and second processor each having a memory test mode wherein they issue commands causing data in at least selected storage locations in the respective memory element to be periodically re-written to those storage locations,

a first switching element that is coupled to the first and second buses and the second memory element, the switching element having a conventional operation mode that couples the second bus to the second memory element, and that has a memory update mode that couples the first bus to the second memory element,

a second switching element that is coupled to the second and first buses and the first memory element, the switching element having a conventional operation mode that couples the first bus to the first memory element, and that has a memory update mode that couples the second bus to the first memory element,

logic that changes a selected one of the first and second switching elements from the conventional operation mode to the memory update during a period in which the second and first processors, respectively, is in the memory test mode.

21. A method of operating a control device, comprising the steps of:

storing data in a first memory element in accord with commands received over a first bus,

storing data in a second memory element in accord with commands received over a second bus,

temporarily coupling both the first memory element and the second memory element to the second bus so that both memory elements store data in accord with commands received over the second bus,

issuing commands on the second bus that cause data in at least selected storage locations in the second memory element to be re-written to those storage locations.

22. The method of claim 21, wherein the step of issuing commands comprises issuing commands on at least the second bus that cause data in at least selected storage locations in the second memory element to be periodically re-written to those storage locations.

23. The method of any of claims 21 and 22, comprising the step of coupling both the first and second memory elements to the second bus for a period sufficient to ensure that substantially all of the selected storage locations in the second memory element are re-written.

24. The method of claim 23, comprising the step of coupling the first memory element to the second bus with an FET switch.

25. The method of claim 23, comprising the step of coupling the first memory element to the second bus with an FET switch array.

26. The method of claim 25, comprising the step of coupling conductors in the second buses to respective conductors of the first memory element wit respective elements of the FET switch array.

27. A method of operating a control device, comprising the steps of:

storing data in a first memory element in accord with commands that are normally received over a first bus,

storing data in a second memory element in accord with commands that are normally received over a second bus,

issuing commands on the second bus causing data in at least selected storage locations in the second memory element to be periodically re-written to those storage locations,

selectively coupling both the first memory element and the second memory element to the second bus and concurrently decoupling the first memory element from the first bus during a period in which the commands are issued on the second bus causing data to be re-written.

28. A method of operating a control device according to claim 27, comprising the steps of

issuing commands on the first bus causing data in at least selected storage locations in the first memory element to be periodically re-written to those storage locations,

in lieu of selectively coupling both the first memory element and the second memory element to the second bus, selectively coupling both the first memory element and the second memory element to the first bus and concurrently decoupling the second memory element from the second bus during a period in which the commands are issued on the first bus causing data to be re-written.

29. The method of claim 28, wherein each element of the FET switch array couples conductors in the first and second buses to respective conductors of a respective one of the memory elements.