Algorithmically programmable memory tester with test sites operating in a slave mode

• US 6,779,140 B2
• Filed: 06/29/2001
• Issued: 08/17/2004
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Agilent Technologies, Inc.
• Inventors: De La Puente, Edmundo, Buck-Gengler, Joel, Krech, Alan S Jr.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): Trimmings, John P.
• Application Number:
  US09/896,474
• Publication Number:
  US 20030005375A1
• Time in Patent Office: 1,145 Days
• Field of Search: 714/718, 324/765, 709/400, 713/400
• US Class Current: 714/718
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A Test Station for a memory tester is comprised of one or more Test Sites that are each individually algorithmically controllable, that can each deal with as many as sixty-four channels, and that can be bonded together to form a Multi-Site Test Station of two or more Test Sites. Up to nine Test Sites can be bonded together as a single Multi-Site Test Station. Bonded Test Sites still operate at the highest speeds they were capable of when not bonded. To bring this about it is necessary to implement certain programming conventions and to provide certain housekeeping functions relating to simultaneous starting of separate test programs on the bonded Test Sites, and relating to propagation and synchronization of test program qualifier results among those separate test programs. There also is a suspend/resume test program execution mechanism that assists one test program in temporarily interrupting the others to allow time for a change within one or more of the Test Sites of a measurement parameter, such as a voltage comparison threshold.

Claims

1. A method of producing in concurrently executing separate programs synchronized responses in those separate programs to an event signal having different propagation delays from its origin to each of respective environments within which each separate program executes, the method comprising the steps of:

(a) executing each separate program on a respectively separate processor, each of which is located within an associated respective electrical environment;

(b) operating corresponding separate counters within the electrical environment for each processor, one value among the counts of which serves as an index signal for the respective electrical environments containing the counters, the counters each operating at the same clock frequency and each having previously been started in unison with a common starting count subsequent to a preceding occurrence of the index signal associated with each counter;

(c) serially propagating an event signal from the electrical environment of one separate processor to another in accordance with an ordering among the separate processors, the serial propagation being in a first direction along the ordering;

(d) in response to the event signal reaching a most distal electrical environment along the ordering in the first direction, generating therein a response signal subsequent to an instance of the index signal for that most distal electrical environment;

(e) serially propagating the response signal, from its origin in the most distal electrical environment along the ordering in the first direction, to each of the other electrical environments, this instance of serial propagation being in a direction along the ordering opposite to that of the first direction of step (c); and

(f) within each electrical environment, responding to the response signal upon the next instance of the index signal from the counter within that electrical environment.

2. A method as in claim 1 wherein step (a) further comprises the steps of operating the respective separate processors with in-phase instances of a common clock frequency, and the responding of step (f) is simultaneous among the respective separate processors.

3. A method as in claim 2 wherein the response of step (f) is the execution of a branching instruction within each separate program.

4. A method as in claim 2 wherein the propagation in step (c) of the event signal is delayed by an electrical environment until an ongoing operation therein is concluded, and the response of step (f) is the resumption of program execution for the separate programs.

5. A method as in claim 1 wherein the counters count down from a selectable starting value and the one value among the counts that serves as the index signal is zero.

6. A method as in claim 1 wherein the separate programs are executed upon test sites within a memory tester for testing a memory that requires more signals than there are channels within a test site.

7. A method of simultaneously commencing execution in concurrent separate programs in response to a start signal having different propagation delays from its origin to each of respective environments within which each separate program executes, the method comprising the steps of:

(a) loading each separate program into the program memory for a respectively separate processor, each of which is located within an associated respective electrical environment and is operated with in-phase instances of a common clock frequency;

(b) operating corresponding separate counters within the electrical environment for each processor, one value among the counts of which serves as an index signal for the respective electrical environments containing the counters, the counters each operating at the same clock frequency and each having previously been started in unison with a common starting count subsequent to a preceding occurrence of the index signal associated with each counter;

(c) serially propagating an arming signal from the electrical environment of one separate processor to another in accordance with an ordering among the separate processors, the serial propagation being in a first direction along the ordering;

(d) in response to the arming signal reaching a most distal electrical environment along the ordering in the first direction, generating therein a start signal subsequent to an instance of the index signal for that most distal electrical environment;

(e) serially propagating the start signal, from its origin in the most distal electrical environment along the ordering in the first direction, to each of the other electrical environments, this instance of serial propagation being in a direction along the ordering opposite to that of the first direction of step (c); and

(f) within each electrical environment, responding to the start signal upon the next instance of the index signal from the counter within that electrical environment by commencing program execution.

8. A method as in claim 7 wherein the counters count down from a selectable starting value and the one value among the counts that serves as the index signal is zero.

9. A method as in claim 7 wherein the separate programs are executed upon test sites within a memory tester for testing a memory that requires more signals than there are channels within a test site.