Process for precise encapsulation of flip chip interconnects

• US 6,780,682 B2
• Filed: 02/22/2002
• Issued: 08/24/2004
• Est. Priority Date: 02/27/2001
• Status: Active Grant

• Current Assignee: Stats Chippac Incorporated (JCET Group Co., Ltd.)
• Original Assignee: Chippac Company Limited
• Inventors: Pendse, Rajendra
• Primary Examiner(s): Pert, Evan
• Assistant Examiner(s): Geyer, Scott B.
• Application Number:
  US10/081,425
• Publication Number:
  US 20020123173A1
• Time in Patent Office: 914 Days
• Field of Search: 438/106, 438/108, 438/118, 438/119, 438/124, 438/126, 438/127, 438/112
• US Class Current: 438/127
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/11822 by dipping, e.g. in a solder bath
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 24/29 of an individual layer connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

A method for encapsulating flip chip interconnects includes applying a limited quantity of encapsulating resin to the interconnect side of an integrated circuit chip, and thereafter bringing the chip together with a substrate under conditions that promote the bonding of bumps on the interconnect side of the chip with bonding pads on the substrate. In some embodiments, the step of applying resin to the chip includes dipping the interconnect side of the chip to a predetermined depth in a pool of resin, and then withdrawing the chip from the resin pool. In some embodiments the step of applying resin to the chip includes providing a reservoir having a bottom, providing a pool of resin in the reservoir to a shallow depth over the reservoir bottom, dipping the chip into the resin pool so that the bumps contact the reservoir bottom, and then withdrawing the chip from the resin pool. Also, apparatus for applying a precise volume of encapsulating resin to a chip, includes a reservoir having a bottom, and means for dispensing a pool of encapsulating resin to a predetermined depth over the reservoir bottom.

Claims

1. A method for encapsulating flip chip interconnects, comprising applying a limited quantity of encapsulating resin to at least interconnect bumps on an interconnect side of a singulated integrated circuit chip, wherein the step of applying resin to the chip comprises providing a reservoir having a bottom and sides, providing a pool of resin in the reservoir to a depth not greater than a bump standoff height, dipping the bumps on the interconnect side of the chip in the resin pool so that bumps on the chip contact the reservoir bottom, and then withdrawing the chip from the resin pool;

and thereafter bringing the chip together with a substrate under conditions that result in displacement of encapsulant from between the bumps on the interconnect side of the chip and respective bonding pads on the substrate, and that promote the bonding of bumps with the respective pads.

2. The method of claim 1 wherein the resin pool depth approximates the bump standoff height.

3. The method of claim 1 wherein the resin pool depth is less than the bump standoff height.

4. A method for encapsulating flip chip interconnects, comprising applying a limited quantity of encapsulating resin to the interconnect side of an integrated circuit chip by providing a pool of resin in a reservoir having a bottom and sides, the resin pool having a depth over the reservoir bottom not greater than about a bump standoff height, dipping the interconnect side of the chip in the pool of resin so that bumps on the chip contact the reservoir bottom and then withdrawing the chip from the resin pool;

and thereafter bringing the chip together with a substrate under conditions that promote the bonding of bumps on the interconnect side of the chip with bonding pads on the substrate.

5. The method of claim 4 wherein the resin pool depth approximates a bump standoff height, so that the surface of the resin pool contacts a surface of the chip, so that as the chip is withdrawn from the resin pool some quantity of resin may remain on the chip surface as well as on features that standoff from the chip surface.

6. The method of claim 4 wherein the resin pool depth is less than the bump standoff height, so that the chip surface does not contact the resin pool, with the result that when the chip is withdrawn from the resin pool some quantity of resin remains only on features that standoff from the chip surface.

7. A method for encapsulating flip chip interconnects, comprising applying a limited quantity of encapsulating resin to the interconnect side of an integrated circuit chip by providing a reservoir having a bottom and sides, the sides defining a reservoir depth not greater than about a bump standoff height, providing a pool of resin in the reservoir, dipping the chip into the resin pool so that bumps on the chip contact the reservoir bottom, and then withdrawing the chip from the resin pool;

and thereafter bringing the chip together with a substrate under conditions that promote the bonding of bumps on the interconnect side of the chip with bonding pads on the substrate.

8. The method of claim 7 wherein the reservoir depth approximates the bump standoff height.

9. The method of claim 7 wherein the reservoir depth is less than the standoff height.