Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

• US 6,780,683 B2
• Filed: 12/06/2002
• Issued: 08/24/2004
• Est. Priority Date: 08/13/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Cleeves, James M., Johnson, Mark G., Knall, Johan
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Vu, David
• Application Number:
  US10/313,763
• Publication Number:
  US 20030124802A1
• Time in Patent Office: 627 Days
• Field of Search: 438/128-131, 438/237-238, 438/268, 438/281, 438/283-284, 438/466-467, 438/484, 438/600, 438/622, 438/637, 257/50, 257/74, 257/202, 257/209, 257/529-530
• US Class Current: 438/128
• CPC Class Codes: G11C 17/16 using electrically-fusible links

Abstract

A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory cells with the adjacent conductors, and each memory cell includes first and second diode components separated by the anti-fuse layer. The diode components form a diode only after the anti-fuse layer is disrupted.

Claims

1. A method for fabricating a memory array comprising:

forming a first conductor level of spaced-apart, parallel, generally coplanar conductors extending in a first direction;

forming a layer stack for defining memory elements on the first conductor level;

patterning the layer stack into a plurality of pillars;

forming a second conductor level of spaced-apart, parallel, generally coplanar conductors extending in a second direction, said second direction not parallel to said first direction;

any of said plurality of pillars comprising an anti-fuse layer, said anti-fuse layer positioned between a pair of diode components that form a diode only after the anti-fuse layer is disrupted.

2. The method of claim 1, wherein any of the conductor levels comprises one or more of:

tungsten,

tantalum,

aluminum, and

copper.

3. The method of claim 2, wherein the memory array comprises a barrier material of one or more of:

titanium nitride,

tantalum, and

tantalum nitride.

4. The method of claim 1, wherein the layer stack comprises:

silicon dioxide; and

a material selected from a group consisting of polysilicon and amorphous silicon.

5. The method of claim 4, wherein any of the conductor levels comprises one or more of:

tungsten,

tantalum,

aluminum, and

copper.

6. The method of claim 5, wherein the memory array comprises a barrier material of one or more of

titanium nitride,

tantalum, and

tantalum nitride.

7. The method of claim 1 wherein the anti-fuse layer comprises silicon dioxide.

8. The method of claim 1 wherein the anti-fuse layer comprises silicon oxynitride.

9. The method of claim 1 wherein a planarization step follows the patterning step.

10. A memory array comprising:

a plurality of first spaced-apart, parallel, substantially coplanar conductors;

a plurality of second spaced-apart, parallel, substantially coplanar conductors disposed vertically above the first conductors;

a plurality of first pillars, each first pillar vertically disposed between one of the first and one of the second conductors;

a plurality of third spaced-apart, parallel, substantially coplanar conductors disposed vertically above the second conductors; and

a plurality of second pillars, each second pillar vertically disposed between one of the second conductors and one of the third conductors,

any of said pillars comprising a respective anti-fuse layer and respective first and second diode components separated by the respective anti-fuse layer,

wherein any of the second conductors forms a top conductor of a lower level of cells and a bottom conductor of a top level of cells,

wherein the memory array is created by a method comprising;

forming the plurality of first conductors;

forming a layer stack on the plurality of first conductors;

patterning the layer stack into the plurality of first pillars; and

forming the plurality of second conductors.