Conformal thin films over textured capacitor electrodes

• US 6,780,704 B1
• Filed: 12/03/1999
• Issued: 08/24/2004
• Est. Priority Date: 12/03/1999
• Status: Expired due to Term

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Raaijmakers, Ivo, Haukka, Suvi P., Granneman, Ernst H. A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Rocchegiani, Renzo
• Application Number:
  US09/452,844
• Time in Patent Office: 1,726 Days
• Field of Search: 438/239-240, 438/243, 438/761-765, 438/780, 438/785, 438/790
• US Class Current: 438/239
• CPC Class Codes: H01L 21/02159 the material containing zirconium, e.g. ZrSiOx
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02183 the material containing tantalum, e.g. Ta2O5
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 21/31691 with perovskite structure
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: Y10T 428/265 1 mil or less

Abstract

Method and structures are provided for conformal capacitor dielectrics over textured silicon electrodes for integrated memory cells. Capacitor structures and first electrodes or plates are formed above or within semiconductor substrates. The first electrodes include hemispherical grain (HSG) silicon for increasing the capacitor plate surface area. The HSG topography is then exposed to alternating chemistries to form monolayers of a desired dielectric material. Exemplary process flows include alternately pulsed metal organic and oxygen source gases injected into a constant carrier flow. Self-terminated metal layers are thus reacted with oxygen. Near perfect step coverage allows minimal thickness for a capacitor dielectric, given leakage concerns for particular materials, thereby maximizing the capacitance for the memory cell and increasing cell reliability for a given memory cell design. Alternately pulsed chemistries are also provided for depositing top electrode materials with continuous coverage of capacitor dielectric, realizing the full capacitance benefits of the underlying textured morphology.

Claims

1. A method of forming a capacitor in an integrated circuit, comprising:

constructing a bottom electrode including a textured silicon layer, the textured silicon layer having hemispherical grain (HSG) morphology; and

depositing a high k dielectric layer directly over the textured silicon layer wherein depositing comprises;

forming no more than about one monolayer of a first material over the textured silicon layer by exposure to a first reactant species;

reacting a second reactant species with the first material to leave no more than about one monolayer of a second material; and

exposing the second material to a third reactant species to leave no more than about one monolayer of a third material, wherein the dielectric layer comprises two different metals and oxygen.

2. The method of claim 1, wherein forming no more than about one monolayer comprises supplying a first chemistry substantially excluding the second reactant species, reacting comprises supplying a second chemistry substantially excluding the first reactant species and exposing comprises supplying a third chemistry substantially excluding the second reactant species.

3. The method of claim 2, further comprising repeatedly alternating supplying the first chemistry, supplying the second chemistry and supplying the third chemistry until a dielectric layer forms having a thickness between about 10 Å

and 200 Å

.

4. The method of claim 2, further comprising supplying a carrier gas while repeatedly alternating supplying the first chemistry, supplying the second chemistry and supplying the third chemistry.

5. The method of claim 4, wherein the carrier gas purges reactants between supplying the first chemistry and supplying the second chemistry and between supplying the second chemistry and supplying the third chemistry.

6. The method of claim 5, wherein supplying the first chemistry is stopped and the reaction chamber is purged with more than about two chamber volumes of purge gas before supplying the second chemistry.

7. The method of claim 1, wherein the dielectric layer comprises a metal, silicon and oxygen.

8. The method of claim 1, wherein the dielectric layer has a dielectric constant of greater than about 10.

9. The method of claim 8, wherein the dielectric layer has a dielectric constant equal to or greater than about 20.

10. The method of claim 1, wherein the first material is self-terminated.

11. The method of claim 10, wherein the first material is terminated by halide ligands.

12. The method of claim 10, wherein the first material is terminated by organic ligands.

13. The method of claim 1, further comprising forming a barrier layer directly on the textured silicon surface prior to forming no more than about one monolayer.

14. The method of claim 13, wherein forming a barrier layer comprises nitriding the textured silicon surface.

15. The method of claim 13, wherein forming a barrier layer comprises oxidizing the textured silicon surface to form a silicon oxide and nitriding the silicon oxide.

16. The method of claim 1, wherein bottom electrode conforms to a three-dimensional folding structure.

17. The method of claim 16, wherein the bottom electrode conforms to a trench within a semiconductor substrate.

18. The method of claim 16, wherein the three-dimensional folding shape is formed above a semiconductor substrate.

19. The method of claim 18, wherein the three-dimensional shape defines an interior volume.

20. The method of claim 19, wherein the three-dimensional shape conforms to a cylinder.

21. The method of claim 1, further comprising depositing a conductive layer over the dielectric layer, wherein depositing the conductive layer comprises:

forming no more than about one monolayer of a fourth material over the dielectric layer by exposure to a fourth reactant species; and

reacting a fifth reactant species with the fourth material to leave no more than about one monolayer of a fifth material.

22. The method of claim 21, wherein the fourth reactant species comprises a metal complex, the fifth reactant species comprises a nitrogen-containing source gas, and the conductive layer comprises a metal nitride.

23. A method of forming a capacitor in an integrated circuit, comprising:

constructing a bottom electrode including a textured silicon layer, the textured silicon layer having hemispherical grain (HSG) morphology; and

depositing a high k dielectric layer directly over the textured silicon layer wherein depositing comprises;

forming no more than about one monolayer of a first material over the textured silicon layer by exposure to a first reactant species, the first material being self-terminated with halide ligands; and

reacting a second reactant species with the first material to leave no more than about one monolayer of a second material, wherein the first reactant species comprises a zirconium halide and the second reactant species comprises an oxygen-containing source gas.

24. A method of forming a capacitor in an integrated circuit, comprising:

constructing a bottom electrode including a textured silicon layer, the textured silicon layer having hemispherical grain (HSG) morphology; and

depositing a high k dielectric layer directly over the textured silicon layer wherein depositing comprises;

forming no more than about one monolayer of a first material over the textured silicon layer by exposure to a first reactant species, the first material being self-terminated with halide ligands; and

reacting a second reactant species with the first material to leave no more than about one monolayer of a second material, wherein the first material comprises ethoxide-terminated tantalum and the second reactant species comprises an oxygen-containing source gas.

25. A method of forming a dielectric layer having a dielectric constant greater than or equal to about 20 directly over a textured silicon bottom electrode having a hemispherical grain (HSG) morphology in an integrated circuit, comprising:

forming no more than about one monolayer of a metal-containing species in a self-limited reaction directly over the textured silicon bottom electrode having a hemispherical grain (HSG) morphology; and

reacting an oxygen-containing species with the monolayer to form the dielectric layer having a dielectric constant greater than or equal to about 20.

26. The method of claim 25, wherein the self-limited reaction comprises forming a halogen-terminated metal film.

27. The method of claim 26, wherein reacting the oxygen-containing species comprises a ligand-exchange reaction.

28. The method of claim 25, further comprising repeating forming no more than about one monolayer and reacting the oxygen-containing species at least about 10 times until the dielectric layer has a desired thickness.

29. A process of forming a capacitor dielectric having a dielectric constant of greater than or equal to about 20 over a hemispherical grain silicon surface, comprising:

directly coating the hemispherical grain silicon surface with no more than about one monolayer of a ligand-terminated metal complex in a first phase;

replacing ligands of the ligand-terminated metal with oxygen in a second phase distinct from the first phase; and

repeating the first and second phases in at least about 10 cycles to form the capacitor dielectric having a dielectric constant of greater than or equal to about 20.

30. The process of claim 29, wherein each cycle comprises a third phase, the third phase comprising adsorbing no more than about one monolayer of a second ligand-terminated metal after the second phase.

31. The process of claim 30, wherein each cycle further comprises a fourth phase, the fourth phase comprising replacing ligands of the second ligand-terminated metal with oxygen.

32. The process of claim 31, wherein the first phase comprises pulsing a first oxygen-containing species.

33. The process of claim 32, wherein the fourth phase comprises pulsing a different oxygen-containing species.

34. The process of claim 29, wherein the ligand-terminated metal comprises a metal chloride complex.

35. The process of claim 29, comprising maintaining a temperature of less than about 350°

C.

36. A process of forming a capacitor dielectric having a dielectric constant of about 10 over a hemispherical grain silicon surface, comprising:

directly coating the hemispherical grain silicon surface with no more than about one monolayer of a ligand-terminated metal complex in a first phase;

replacing ligands of the ligand-terminated metal with oxygen in a second phase distinct from the first phase; and

repeating the first and second phases in at least about 10 cycles, wherein the ligand-terminated metal comprises a metal ethoxide complex.

37. A method of forming a capacitor with high surface area in an integrated circuit, comprising:

forming a bottom electrode in a three-dimensional folding shape;

superimposing a hemispherical grain silicon layer over the three-dimensional folding shape; and

depositing a high k dielectric layer conformally directly over the textured morphology by cyclically supplying at least three alternating, self-terminating chemistries, wherein no more than one monolayer is formed per cycle, and wherein the dielectric layer comprises silicon, oxygen and a metal.

38. A method of forming a capacitor in an integrated circuit, comprising:

constructing a bottom electrode including a textured silicon layer, the textured silicon layer having hemispherical grain (HSG) morphology; and

depositing a high k dielectric layer directly over the textured silicon layer wherein depositing comprises;

forming no more than about one monolayer of a first material over the textured silicon layer by exposure to a first reactant species; and

reacting a second reactant species with the first material to leave no more than about one monolayer of a second material, and

wherein the dielectric layer is selected from the group consisting of tantalum oxide, titanium oxide, zirconium oxide, niobium oxide, hafnium oxide and mixtures and compounds thereof.