Vertically stacked field programmable nonvolatile memory and method of fabrication

• US 6,780,711 B2
• Filed: 09/23/2002
• Issued: 08/24/2004
• Est. Priority Date: 11/16/1998
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Subramanian, Vivek, Lee, Thomas H., Farmwald, Paul Michael, Johnson, Mark G.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, LONG K
• Application Number:
  US10/253,354
• Publication Number:
  US 20030026121A1
• Time in Patent Office: 701 Days
• Field of Search: 438/257, 438/128-132, 438/197, 438/210, 438/275, 438/278, 438/279, 438/289, 438/467, 438/600, 438/601, 257/390, 257/391
• US Class Current: 438/257
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Claims

1. A method of fabricating a memory array comprising:

forming a first conductor level of spaced-apart, parallel, generally coplanar conductors extending in a first direction;

depositing a layer stack, then patterning and etching said layer stack to form a first pillar level of pillars,

forming a second conductor level of spaced-apart, parallel, generally coplanar conductors above the first pillar level, the conductors of said second conductor level extending in a second direction, said second direction not parallel to said first direction,

wherein the pillars of the first pillar level are vertically disposed between the conductors of the first conductor level and the conductors of the second conductor level.

2. The method of claim 1, further comprising:

following the step of forming the first pillar level of pillars, depositing and planarizing an insulating material.

3. The method of claim 1, wherein the pillars comprise a state-change element.

4. The method of claim 1, wherein the pillars comprise a steering element.

5. The method of claim 1, wherein the memory array is a write-once memory array.

6. The method of claim 1 wherein any of the conductors comprises one or more of tungsten and aluminum.

7. The method of claim 6, wherein the memory array comprises a barrier material of one or more of:

titanium nitride,

tantalum and

tantalum nitride.

8. The method of claim 1 wherein any of the pillars comprises an antifuse.

9. The method of claim 8 wherein the antifuse comprises silicon dioxide.

10. A memory array created by a method, the method comprising:

forming a first conductor level of spaced-apart, parallel, generally coplanar conductors extending in a first direction;

depositing a layer stack, then patterning and etching said layer stack to form a first pillar level of pillars;

forming a second conductor level of spaced-apart, parallel, generally coplanar conductors above the first pillar level, the conductors of said second conductor level extending in a second direction, said second direction not parallel to said first direction,

wherein the pillars of the first pillar level are vertically disposed between the conductors of the first conductor level and the conductors of the second conductor level.

11. The memory array of claim 10 further comprising:

following the step of forming the first pillar level of pillars, depositing and planarizing an insulating material.

12. The memory array of claim 10, wherein the pillars comprise a state-change element.

13. The memory array of claim 10, wherein the pillars comprise a steering element.

14. The memory array of claim 10, wherein the memory array is a write-once memory array.

15. The memory array of claim 10, wherein any of the conductors comprises one or more of tungsten and aluminum.

16. The memory array of claim 15, wherein the memory array comprises a barrier material of one or more of

titanium nitride,

tantalum and

tantalum nitride.

17. The memory array of claim 10 wherein any of the pillars comprises an antifuse.

18. The memory array of claim 17 wherein the antifuse comprises silicon dioxide.