Process for manufacturing a DMOS transistor

• US 6,780,713 B2
• Filed: 06/11/2002
• Issued: 08/24/2004
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Original Assignee: Atmel Germany GmbH (Microchip Technology Incorporated)
• Inventors: Graf, Michael, Dietz, Franz, Dudek, Volker, Bromberger, Christoph, Klaussner, Manfred, Herrfurth, Joern
• Primary Examiner(s): Pham, Long
• Assistant Examiner(s): TRINH, HOA B
• Application Number:
  US10/167,959
• Publication Number:
  US 20030001198A1
• Time in Patent Office: 805 Days
• Field of Search: 438/202, 438/234, 438/212, 438/289, 438/306, 438/199, 438/259, 438/250, 438/270, 438/271, 438/242, 438/238, 257/335, 257/336, 257/339, 257/343
• US Class Current: 438/270
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

Claims

1. A process for manufacturing a DMOS transistor (100) with a semiconductor body (5), which features a surface layer with a source region (10) and a drain region (80) of a second conductivity type, and a first veil region (20) of a first conductivity type enclosing the source region (10), and a second well region (19) of a second conductivity type enclosing the drain region, wherein a gate region (35) is formed on the surface of the surface layer of the semiconductor body (5), which gate region extends from the source region across the first well region (20),

said method comprising:

starting on the surface of the semiconductor body (5), forming a trench-shaped structure in the surface layer, such that the trench-shaped structure includes a floor region, a source-end side wall extending from the floor region to the surface on a first side of the trench-Shaped structure proximate to the source region, and a drain-end side wall on a second side of the trench-shaped structure proximate to the drain region, wherein at least one of the side walls slopes non-perpendicularly relative to the surface so that the trench-shaped structure has a tapering cross-section with a greater width at the surface than at the floor region;

producing a doping of the second conductivity type with a first concentration value in the floor region of the trench-shaped structure;

producing a doping of the second conductivity type with a second concentration value in the source-end side wall of the trench-shaped structure; and

producing a doping of the second conductivity type with a third concentration value in the drain-end side wall of the trench-shaped structure.

2. The process according to claim 1, wherein the trench-shaped structure is produced partially or wholly within the second well region (19).

3. The process according to claim 1, further comprising producing an extension region (70) of a second conductivity type which encloses the drain region (80) below the drain region.

4. The process according to claim 2, further comprising producing an extension region (70) of a second conductivity type which encloses the drain region (80) below the drain region.

5. The process according to claim 1, further comprising producing the drain region (80) immediately adjacent to the drain-end side wall of the trench-shaped structure.

6. The process according to claim 4, wherein further comprising producing the drain region (80) immediately adjacent to the drain-end side wall of the trench-shaped structure.

7. The process according to claim 4, wherein the extension region (70) is produced immediately adjacent to the drain-end side wall of the trench-shaped structure.

8. The process according to claim 4, wherein the drain region (80) and the extension region (70) are produced immediately adjacent to the drain-end side wall of the trench-shaped structure.

9. The process according to claim 4, further comprising producing a spacing distance between the drain-end side wall of the trench-shaped structure and the extension region (70), wherein the spacing distance is between 0.5 μ

m and 4.0 μ

m.

10. The process according to claim 1, further comprising producing a spacing distance between the drain-end side wall of the trench-shaped structure and the drain region (80), wherein the spacing distance is between 0.5 μ

m and 4.0 μ

m.

11. The process according to claim 4, further comprising producing a spacing distance between the drain-end side wall of the trench-shaped structure, and the drain region (80), wherein the spacing distance is between 0.5 μ

m and 4.0 μ

m.

12. The process according to claim 4, further comprising producing a spacing distance between the drain-end side wall of the trench-shaped structure and the extension region (70), and between the drain-end side wall and the drain region (80), wherein the spacing distance is between 0.5 μ

m and 4.0 μ

m.

13. The process according to claim 1, wherein the first concentration value, the second concentration value, and the third concentration value are each higher than a doping concentration level in the first well region (20).

14. The process according to claim 8, wherein the first concentration value, the second concentration value, and the third concentration value are each higher than a doping concentration level in the semiconductor body (5) and/or the first well region (20).

15. The process according to claim 12, wherein the first concentration value, the second concentration value, and the third concentration value are each higher than a doping concentration level in the semiconductor body and/or a the first well region (20).

16. The process according to claim 1, wherein the second and third concentration values are equal.

17. The process according to claim 8, wherein the second and third concentration value are equal.

18. The process according to claim 12, wherein the second and third concentration values are equal.

19. The process according to claim 1, wherein the second concentration value is lower than the third concentration value.

20. The process according to claim 8, wherein the second concentration value is lower than the third concentration value.

21. The process according to claim 12, wherein the second concentration value is lower than the third concentration value.

22. The process according to claim 1, wherein the trench-shaped structure is produced so as to have an aspect ratio above 0.5 and a width between 0.5 μ

m and 4.0 μ

m.

23. The process according to claim 1, wherein the trench-shaped structure is produced by STI etchings, and further comprising filling the trench-shaped structure with an isolating material, comprising an oxide.

24. The process according to claim 1, wherein the trench-shaped structure is produced by LOCOS oxidation.

25. The process according to claim 1, wherein the semiconductor body further features an isolating intermediate layer (4) below the surface layer, and the DMOS transistor is produced in the surface layer.

26. The process according to claim 25, wherein a portion of the surface layer between the trench-shaped structure and the intermediate layer has a thickness between one half and five times a depth of the trench-shaped structure.

27. The process according to claim 1, wherein a portion of the surface layer underneath the trench-shaped structure has a thickness between one half and five times a depth of the trench-shaped structure.

28. The process according to claim 1, wherein the two well regions (19, 20), and the source region (10), and at least one of the drain region (80) and the extension region (70), are each produced immediately adjacent to the isolating intermediate layer (4).

29. The process according to claim 1, wherein the first concentration value in the floor region is independent from and greater than at least one of the second and third concentration values in the side walls.

30. The process according to claim 1, wherein the third concentration value in the drain-end side wall is higher than the first concentration value in the floor region, which is higher than the second concentration value in the source-end side wall.

31. The process according to claim 1, wherein at least some of the doping in the side walls is produced by implantation before forming the trench-shaped structure.

32. The process according to claim 31, wherein at least some of the doping in the side walls, and the doping in the floor region are produced by implantation after forming the trench-shaped structure.

33. The process according to claim 1, wherein at least some of the doping in the side walls, and the doping in the floor region are produced by implantation after forming the trench-shaped structure.

34. The process according to claim 1, further comprising forming an oxide protective layer on the side walls before producing the doping in the floor region by dopant implantation.

35. The process according to claim 1, wherein the doping of the second conductivity type is produced respectively in the entire side walls and in the entire floor region.

36. The process according to claim 1, further comprising forming the first and second well regions laterally next to each other and not stacked on top of one another, and forming the source region directly over and bordering on the first well region and not over the second veil region, end forming the drain region over the second veil region and not over the first well region, and forming the a trench-shaped structure enclosed in and surrounded by the second well, region.

37. A process of manufacturing a DMOS transistor, comprising the steps:

a) providing a semiconductor body having a surface;

b) etching a trench into said semiconductor body from said surface, so that said trench is bounded by a floor and first and second side walls extending from said surface to said floor, wherein said first and second side walls are non-parallel relative to each other and said trench has a tapering cross-section with a greater width between said first and second side walls at said surface than at said floor;

c) implanting a dopant into said semiconductor body to result in a first dopant concentration of said dopant in a first wail region of said semiconductor body along a location of said first side wall, a second dopant concentration of said dopant in a second wall region of said semiconductor body along a location of said second side wall, and a third dopant concentration of said dopant in a floor region of said semiconductor body along a location of said floor;

d) forming in said semiconductor body a source region adjacent to said location of said first aids wall;

e) forming in maid semiconductor body a drain region adjacent to said location of said second side wall;

f) forming in said semiconductor body a first well region of a first conductivity type at a location underlying said source region;

g) forming in said semiconductor body a second well region of a second conductivity type at a location underlying said drain region; and

h) forming a gate structure on said surface of said semiconductor body and adjoining said source region.

38. The process according to claim 37, further comprising forming an oxide protective layer on said side walls after said step b) and before at least said implanting of said dopant into said floor region in said step c).

39. The process according to claim 37, wherein said implanting of said dopant in said step c) is carried out partially before said step b) and partially after said step b).

40. The process according to claim 37, wherein said implanting of said dopant in said step c) comprises implanting said dopant at least into said first wall region and said second wall region in said semiconductor body before said etching of said trench in said step b), and then performing said etching to form said first side wall along said first wall region and to farm said second side wall along said second wall region.

41. The process according to claim 40, wherein said implanting of said dopant before said step b) is performed at a non-perpendicular inclined angle relative to said surface of said semiconductor body.

42. The process according to claim 40, wherein said a implanting of said dopant in said step c) further comprises implanting said dopant into said floor region and additionally into at least said second wall region in said semiconductor body after said etching of said trench in said step b).

43. The process according to claim 37, wherein said implanting of said dopant in said step c) comprises implanting said dopant into at least said floor region in said semiconductor body after said etching of said trench in said step b).

44. The process according to claim 43, further comprising a forming an oxide protective layer on said side walls after said step b) and before said implanting of said dopant into said floor region.

45. The process according to claim 43, wherein said a implanting of said dopant after said etching of said trench in said step b) comprises a first implantation of said dopant oriented perpendicular to said surface into said floor region, and a second implantation of said dopant a oriented at a non-perpendicular inclined angle relative to said surface into said second wall region.

46. The process according to claim 37, wherein said implanting of said dopant is carried out so that said second dopant concentration in said second wall region is higher than said first dopant concentration in said first wall region.

47. The process according to claim 46, wherein said third dopant concentration in said floor region is between said first and second dopant concentrations.

48. A process of manufacturing a DMOS transistor, comprising the steps:

a) providing a semiconductor body having a surface;

b) implanting a first dopant into said semiconductor body to form a first doped region that is doped with said first dopant;

c) after said step b), etching a trench from said surface into said first doped region in said semiconductor body, so that said trench is bounded by a floor along a floor region in said semiconductor body, a first side wall extending from said surface to said floor along a first wall region having a first dopant concentration of said first dopant within said first doped region, and a second side wall extending from said surface to said floor along a second wall region having a second dopant concentration of said first dopant within said first doped region;

d) after said step c), implanting a second dopant through said trench into said floor region so as to produce a third dopant concentration of said second dopant in said floor region;

e) forming in said semiconductor body a source region adjacent to a location of said first side wall;

f) forming in said semiconductor body a drain region adjacent to a location of said second side wall;

g) forming in said semiconductor body a first well region of a first conductivity type at a location underlying said source region;

h) forming in said semiconductor body a second well region of a second conductivity type at a location underlying said drain region; and

i) forming a gate structure on said surface of said semiconductor body and adjoining said source region.

49. The process according to claim 48, further comprising forming an oxide protective layer on said side walls after said step c) and before said step d).