Method for fabricating a nitrided silicon-oxide gate dielectric

• US 6,780,720 B2
• Filed: 07/01/2002
• Issued: 08/24/2004
• Est. Priority Date: 07/01/2002
• Status: Expired due to Term

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Furukawa, Toshiharu, Chou, Anthony I., Nakos, James S., Burnham, Jay S., Gibson, Margaret L., Shank, Steven M.
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US10/187,572
• Publication Number:
  US 20040002226A1
• Time in Patent Office: 785 Days
• Field of Search: 438/301, 438/775, 438/786, 438/287, 438/787, 438/776
• US Class Current: 438/287
• CPC Class Codes: H01L 21/0214 the material being a silicon oxynitride, e.g. SiON or SiON:H
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Abstract

A method of fabricating a gate dielectric layer. The method comprises: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; exposing the silicon dioxide layer to a plasma nitridation to convert the silicon dioxide layer into a silicon oxynitride layer; and performing a spiked rapid thermal anneal of the silicon oxynitride layer.

Claims

1. A method or fabricating a gate dielectric layer, comprising:

providing a substrate;

forming a silicon dioxide layer on a top surface of said substrate;

selecting a nitrogen flow rate in dependence upon a thickness of the silicon dioxide layer;

exposing said silicon dioxide layer to a plasma nitridation to convert said silicon dioxide layer into a silicon oxynitride layer; and

performing a spiked rapid thermal anneal of said silicon oxynitride layer,

wherein said exposing is performed using a decoupled plasma process; and

wherein said exposing is performed using a flowing mixture of nitrogen and an inert gas such that the nitrogen flows at the nitrogen flow rate.

2. The method of claim 1, wherein said silicon dioxide layer has a thickness of 20 Å

or less.

3. The method of claim 1, wherein said performing a spiked rapid thermal anneal includes reaching a maximum temperature of between 800 and 1300°

C. and maintaining said maximum temperature for between 0 and 60 seconds.

4. The method of claim 1, wherein said substrate includes a bulk silicon or silicon on a insulator substrate and said forming a silicon dioxide layer is formed by a process selected from the group consisting of thermal oxidation, rapid thermal oxidation and chemical vapor deposition.

5. The method of claim 1, wherein said silicon oxynitride film contains between 5 and 15% nitrogen atoms.

6. The method of claim 1, wherein said silicon dioxide layer contains between 0 and 5 atomic percent nitrogen before said exposing said silicon dioxide layer to a plasma nitridation to convert said silicon dioxide layer into a silicon oxynitride layer.

7. The method of claim 1, wherein said silicon dioxide nitride layer is less than 23 Å

thick.

8. The method of claim 1, wherein the concentration of nitrogen in said silicon oxynitride layer is between 1E21 and 5E21 atm/cm³.

17. The method of claim 1, further comprising selecting an inert gas flow rate in dependence upon the thickness of the silicon dioxide layer, wherein during said exposing the inert gas flows or the inert gas flow rate.

18. The method of claim 17, further comprising selecting a power level for the decoupled plasma process in dependence upon the thickness of the silicon dioxide layer, wherein said exposing is performed using the decoupled plasma process power level.

19. The method of claim 1, further comprising selecting a power level for the decoupled plasma process in dependence upon the thickness of the silicon dioxide layer, wherein said exposing is performed using the decoupled plasma process power level.

9. A method of fabricating a MOSFET, comprising:

providing a silicon substrate;

forming a silcon dioxide layer on a top surface of said silicon substrate;

selecting a nitrogen flow rate in dependence upon a thickness of the silicon dioxide layer;

exposing said silicon dioxide layer to a plasma nitridation to convert said silicon dioxide layer to a silicon oxynitride layer;

performing a spiked rapid thermal anneal of said silicon oxynitride layer;

forming a polysilicon gate on said anneal silicon oxynitride layer aligned over a channel region in said silicon substrate; and

forming source/drain regions in said silicon substrate, and source drain regions aligned to said polysilicon gate, wherein said exposing is performed using a decoupled plasma process; and

wherein said exposing is performed using a flowing mixture of nitrogen and an inert gas such that the nitrogen flows at the nitrogen flow rate.

10. The method of claim 9, wherein said silicon dioxide layer has a thickness of 20 Å

or less.

11. The method of claim 9 wherein said performing a spiked rapid thermal anneal includes reaching a maximum temperature of between 800 and 1300°

C. and maintaining said maximum temperature for between 0 and 60 seconds.

12. The method of claim 9, wherein said substrate is a bulk silicon substrate or silicon on insulator substrate and said forming a silicon dioxide layer is formed by a process selected from the group consisting of thermal oxidation, rapid thermal oxidation and chemical vapor deposition.

13. The method of claim 9 wherein said polysilicon gate is between 1000 and 2000 Å

thick.

14. The method of claim 9, wherein said silicon dioxide layer contains between 0 and 5 atomic percent nitrogen before said exposing said silicon dioxide layer to a plasma nitridation to convert said silicon dioxide layer into a silicon oxynitride layer.

15. The method of claim 9, wherein said silicon dioxide nitride layer is less then 23 Å

thick.

16. The method of claim 9, wherein the concentration of nitrogen in said silicon oxynitride layer is between 1E21 and 5E21 atm/cm³.

20. The method of claim 9, further comprising selecting an inert gas flow rate in dependence upon the thickness of the silicon dioxide layer, wherein during said exposing the inert gas flows at the inert gas flow rate.

21. The method of claim 20, further comprising selecting a power level for the decoupled plasma process in dependence upon the thickness of the silicon dioxide layer, wherein said exposing is performed using the decoupled plasma process power level.

22. The method of claim 9, further comprising selecting a power level for the decoupled plasma process in dependence upon the thickness of the silicon dioxide layer, wherein said exposing is performed using the decoupled plasma process power level.