Method for stacking semiconductor die within an implanted medical device

• US 6,780,770 B2
• Filed: 12/13/2000
• Issued: 08/24/2004
• Est. Priority Date: 12/13/2000
• Status: Expired due to Fees

• Current Assignee: Medtronic Incorporated (Medtronic Plc)
• Original Assignee: Medtronic Incorporated (Medtronic Plc)
• Inventors: Larson, Lary R.
• Primary Examiner(s): Norton, Nadine G.
• Assistant Examiner(s): UMEZ ERONINI, LYNETTE T
• Application Number:
  US09/735,826
• Publication Number:
  US 20020123233A1
• Time in Patent Office: 1,350 Days
• Field of Search: 438/689, 438/692, 438/703, 438/712, 438/700, 438/706
• US Class Current: 438/689
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A method for forming a stackable wafer for use in an implantable device is provided. The method comprises forming an opening extending substantially through the wafer. Thereafter, conductive material is deposited within the opening to substantially fill the opening. A bump is then formed on an upper surface of the wafer adjacent the conductive material, and a contact pad is formed on a lower surface of the wafer adjacent the conductive material. A second wafer formed using substantially the same process may then be stacked on top of the first wafer with the bump of the first wafer being in contact with the contact pad of the second wafer. A soldering process may then be used to couple the adjacent pad and wafer for physically mounting the wafers and providing electrical connectivity therebetween.

Claims

1. A method for forming a stackable wafer in an implantable device, comprising:

forming an opening extending substantially through the wafer;

depositing conductive material within the opening to substantially fill the opening;

forming a bump on and extending outward from an upper surface of the wafer adjacent the conductive material; and

forming a contact pad on and extending outward from a lower surface of the wafer adjacent the conductive material.

2. The method set forth in claim 1, wherein forming an opening further comprises exposing a selected portion of the upper surface of the wafer to a reactive ion etching process for a preselected duration of time.

3. The method set forth in claim 1, wherein depositing conductive material within the opening further comprises depositing at least one of copper, tungsten, nickel, and aluminum within the opening.

4. The method set forth in claim 1, wherein depositing conductive material within the opening further comprises depositing a layer of conductive material over the upper surface of the wafer and within the opening, and removing a portion of the layer of conductive material overlying the upper surface of the wafer.

5. The method set forth in claim 4, wherein removing a portion of the layer of conductive material further comprises performing a chemical mechanical polishing of the layer of conductive material to remove a portion of the layer of conductive material overlying the upper surface of the wafer.

6. The method of claim 1, wherein forming a bump on an upper surface of the wafer further comprises forming a bump wherein at least a portion of a surface of the bump is wettable.

7. The method of claim 1, wherein forming a contact pad on a lower surface of the wafer further comprises forming a contact pad wherein at least a portion of a surface of the contact pad is wettable.

8. The method of claim 1, wherein forming an opening extending substantially through the wafer further comprises forming the opening extending substantially through a substrate of the wafer.

9. The method of claim 8, wherein forming an opening extending substantially through the wafer further comprises forming the opening extending substantially through a substrate of the wafer and any additional process layers formed on the substrate.

10. The method set forth in claim 1, wherein depositing conductive material within the opening further comprises depositing conductive material in contact with at least one conductive layer disposed within the wafer.

11. A method for forming a stacked arrangement of a first and second wafer in an implantable device, comprising:

forming an opening extending substantially through the first wafer;

depositing conductive material within the opening to substantially fill the opening in the first wafer;

forming a bump on an upper surface of the first wafer adjacent the conductive material;

forming a contact pad on a lower surface of the first wafer adjacent the conductive material;

forming an opening extending substantially through the second wafer, depositing conductive material within the opening to substantially fill the opening in the second wafer;

forming a bump on an upper surf ace of the second wafer adjacent the conductive material;

forming a contact pad on a lower surface of the second wafer adjacent the conductive material;

positioning the first water adjacent the second wafer with the bump of the first wafer being adjacent the contact pad of the second wafer; and

coupling the bump of the first wafer with the contact pad of the second wafer.

12. The method set forth in claim 11, wherein coupling the bump of the first wafer with the contact pad of the second wafer further comprises soldering the bump of the first wafer with the contact pad of the second wafer.

13. The method set forth in claim 11, wherein forming an opening in the first wafer further comprises exposing a selected portion of the upper surface of the first wafer to a reactive ion etching process for a preselected duration of time.

14. The method set forth in claim 11, wherein depositing conductive material within the opening of the first wafer further comprises depositing at least one of copper, tungsten, nickel, and aluminum within the opening of the first wafer.

15. The method set forth in claim 11, wherein depositing conductive material within the opening of the first wafer further comprises depositing a layer or conductive material over the upper surface of the first wafer and within the opening, and removing a portion of the layer of conductive material overlying the upper surface of the first wafer.

16. The method set forth in claim 15, wherein removing a portion of the layer of conductive material further comprises performing a chemical mechanical polishing of the layer of conductive material to remove a portion of the layer of conductive material overlying the upper surface of the first wafer.

17. The method of claim 11, wherein forming a bump on an upper surface of the first wafer further comprises forming a bump wherein at least a portion of a surface of the bump is wettable.

18. The method of claim 11, wherein forming a contact pad on a lower surface of the second wafer further comprises forming a contact pad wherein at least a portion of a surface of the contact pad is wettable.

19. The method of claim 11, wherein forming an opening extending substantially through the firs wafer further comprises forming the opening extending substantially through a substrate of the first wafer.

20. The method of claim 19, wherein forming an opening extending substantially through the first wafer further comprises forming the opening extending substantially through the substrate of the first wafer and any additional process layers formed on the substrate.

21. The method set forth in claim 11, wherein depositing conductive material within the opening of the first wafer further comprises depositing conductive material in contact with at least one conductive layer disposed within the first wafer.

22. A method for forming a stackable wafer for use in an implantable medical device, comprising:

providing a housing;

mounting a semiconductor module inside the housing, wherein said semiconductor module includes first and second semiconductor die in a stacked arrangement, the stacked semiconductor die having circuitry implementing an operational implantable medical device function; and

providing a plurality of electrical connections extending between the die, each electrical connection comprising an interconnection between a bump on an upper surface that extends outward from the upper surface of the first die and a contact pad on a lower surface that extends outward from the lower surface of the second die.

23. The method of claim 22 further comprises a solder connection that is provided for the interconnection between a bump on an upper surface of the first die and a contact pad on a lower surface of the second die.

24. The method of claim 22 further comprises delivering electrical stimulation therapy via said circuitry.

25. The method of claim 22 wherein an operational implantable medical device function further comprises pacing and sensing functions that are implemented by the circuitry.