Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer

• US 6,780,776 B1
• Filed: 12/20/2001
• Issued: 08/24/2004
• Est. Priority Date: 12/20/2001
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Michael, Mark W., Qi, Wen-Jie, Pellerin, John G., En, William G., Chan, Darin A.
• Primary Examiner(s): Norton, Nadine G.
• Assistant Examiner(s): Vinh, Lan
• Application Number:
  US10/023,328
• Time in Patent Office: 978 Days
• Field of Search: 438/283, 438/287, 438/290, 438/301, 438/306, 438/706, 438/710, 438/712, 438/720
• US Class Current: 438/706
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.

Claims

1. A method of forming a semiconductor device, comprising the steps of:

forming a gate electrode on a substrate;

forming a polysilicon reoxidation layer over the substrate and the gate electrode;

depositing a nitride layer over the polysilicon reoxidation layer;

anisotropically etching the nitride layer and stopping on the polysilicon reoxidation layer to form nitride offset spacers on the gate electrode; and

forming source/drain extensions in the substrate after the nitride layer has been etched, subsequently forming sidewall spacers on the offset spacers, and forming source/drains in the substrate.

2. The method of claim 1, further comprising forming halo implants in the substrate prior to depositing the nitride layer.

3. The method of claim 1, wherein the anisotropic etching is performed with a reactive ion etch process with a high nitride to oxide selectivity.

4. The method of claim 3, wherein the step of forming a polysilicon reoxidation layer comprises thermally growing oxide on the substrate and the gate electrode at temperatures between about 700°

C. to about 900°

C.

5. The method of claim 4, wherein the polysilicon reoxidation layer is between about 15Å

to about 50Å

thick.

6. The method of claim 5, wherein the step of anisotropically etching the nitride layer includes reactive ion etching with CHF₃ plasma etch gas.

7. The method of claim 6, further comprising removing the exposed polysilicon reoxidation layer after the nitride layer has been etched and prior to forming source/drain extensions in the substrate.

8. The method of claim 7, wherein the removing of the exposed polysilicon reoxidation layer includes wet etching the exposed polysilicon reoxidation layer.

9. The method of claim 8, wherein the exposed polysilicon reoxidation layer is wet etched with 100:

1 HF solution.

10. A method of forming a semiconductor device with halo implants, comprising the steps of:

forming a gate electrode on a substrate;

forming an etch stop layer on the substrate;

forming a nitride layer on the etch stop layer;

etching the nitride layer to form offset spacers on the gate electrode, and stopping the etching on the etch stop layer;

forming halo implants in the substrate; and

;

forming source/drain extensions and source/drain implants by implantation through the polysilicon reoxidation layer after the nitride layer has been etched.

11. The method of claim 10, wherein the step of etching the nitride layer includes reactive ion etching the nitride layer with a plasma etchant gas that has a high nitride to oxide selectivity.

12. The method of claim 10, wherein the etch stop layer is a polysilicon reoxidation layer.

13. The method of claim 10, further comprising removing portions of the polysilicon reoxidation layer exposed by the etching of the nitride layer to thereby expose the substrate.

14. The method of claim 13, wherein the step of removing portions of the polysilicon reoxidation layer includes wet etching.

15. The method of claim 14, wherein the step of etching the nitride layer includes reactive ion etching the nitride layer with a plasma etchant gas that has a high nitride to oxide selectivity.