Low dielectric constant shallow trench isolation
First Claim
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1. A memory device, comprising:
- an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench contains cells of gaseous components;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit.
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Abstract
Techniques of shallow trench isolation and devices produced therefrom. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.
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Citations
30 Claims
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1. A memory device, comprising:
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an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench contains cells of gaseous components;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit. - View Dependent Claims (2, 3, 4)
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5. A memory device, comprising:
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an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with a foamed polymeric material;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A memory device, comprising:
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an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with a cured aerogel;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit. - View Dependent Claims (12, 13)
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14. A memory device, comprising:
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an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with an air gap;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit. - View Dependent Claims (15, 16, 17)
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18. A memory module, comprising:
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a support;
a plurality of leads extending from the support;
a command link coupled to at least one of the plurality of leads;
a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and
at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises;
an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench contains cells of gaseous components;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit. - View Dependent Claims (19, 20, 21)
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22. A memory module, comprising:
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a support;
a plurality of leads extending from the support;
a command link coupled to at least one of the plurality of leads;
a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and
at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises;
an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with a foamed polymeric material;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit. - View Dependent Claims (23, 24, 25)
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26. A memory module, comprising:
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a support;
a plurality of leads extending from the support;
a command link coupled to at least one of the plurality of leads;
a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and
at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises;
an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with a cured aerogel;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit. - View Dependent Claims (27, 28)
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29. A memory module, comprising:
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a support;
a plurality of leads extending from the support;
a command link coupled to at least one of the plurality of leads;
a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and
at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises;
an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with an air gap;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit. - View Dependent Claims (30)
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Specification