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Low dielectric constant shallow trench isolation

  • US 6,781,192 B2
  • Filed: 06/27/2002
  • Issued: 08/24/2004
  • Est. Priority Date: 02/14/2000
  • Status: Expired due to Term
First Claim
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1. A memory device, comprising:

  • an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench contains cells of gaseous components;

    a row access circuit coupled to the array of memory cells;

    a column access circuit coupled to the array of memory cells; and

    an address decoder circuit coupled to the row access circuit and the column access circuit.

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