Trench DMOS transistor having improved trench structure

• US 6,781,196 B2
• Filed: 03/11/2002
• Issued: 08/24/2004
• Est. Priority Date: 03/11/2002
• Status: Expired due to Fees

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, So, Koon Chong, Tsui, Yan Man
• Primary Examiner(s): Jackson, Jerome
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US10/094,932
• Publication Number:
  US 20030168696A1
• Time in Patent Office: 897 Days
• Field of Search: 257/327-335
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench DMOS transistor cell is provided that includes a substrate of a first conductivity type and a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and a conductive electrode is placed in the trench overlying the insulating layer. A source region of the first conductivity type is located in the body region adjacent to the trench. The trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees.

Claims

1. A trench DMOS transistor structure that includes a plurality of individual trench DMOS transistor cells formed on a substrate of a first conductivity type, each of said individual trench DMOS transistor cells comprising:

a body region on the substrate, said body region having a second conductivity type;

at least one trench extending through the body region and the substrate;

an insulating layer that lines the trench;

a conductive electrode in the trench overlying the insulating layer;

a source region of the first conductivity type in the body region adjacent to the trench;

a plurality of polysilicon contacts respectively connected to transistor cells located along the periphery of the structure; and

a polysilicon trench guard ring coupling together said plurality of polysilicon contacts,

wherein said trench has sidewalls that define a polygon in the plane of the substrate so that adjacent sidewalls contact one another at an angle greater than 90 degrees,

and wherein the sidewalls comprise at least a first pair of parallel sidewalls and a second pair of parallel sidewalls, the first pair of parallel sidewalls lying in a first plane, and the second pair of parallel sidewalls lying in a second plane, the first and second planes at right angles to each another,

wherein the first pair of parallel sidewalls and the second pair of parallel sidewalls do not directly contact one another.

2. The DMOS transistor structure of claim 1 further comprising a drain electrode disposed on a surface of the substrate opposing the body region.

3. The DMOS transistor structure of claim 1 wherein said insulating layer is an oxide layer.

4. The DMOS transistor structure of claim 1 wherein said conductive electrode includes polysilicon.

5. The DMOS transistor structure of claim 4 wherein said polysilicon includes a dopant material.

6. The DMOS transistor structure of claim 4 wherein said polysilicon includes a layer of undoped polysilicon and a layer of doped polysilicon.

7. The DMOS transistor structure of claim 6 wherein said polygon is an octagon and said angle is equal to 135 degrees.

8. The DMOS transistor structure of claim 1 wherein at least one of said trench DMOS transistor cells have a closed cell geometry.

9. The DMOS transistor structure of claim 8 further comprising a plurality of polysilicon contacts respectively connected to transistor cells located along the periphery of the structure.

10. The DMOS transistor structure of claim 9 further comprising a polysilicon trench guard ring coupling together said plurality of polysilicon contacts.

11. The DMOS transistor structure of claim 1 wherein at least one of said trench DMOS transistor cells have an open cell geometry.

12. The DMOS transistor structure of claim 11 further comprising a plurality of polysilicon contacts respectively connected to transistor cells located along the periphery of the structure.

13. The DMOS transistor structure of claim 12 further comprising a polysilicon trench guard ring coupling together said plurality of polysilicon contacts.

14. The DMOS transistor structure of claim 1 wherein said polygon is an octagon and said angle is equal to 135 degrees.