Semiconductor device having first and second trenches with no control electrode formed in the second trench

• US 6,781,199 B2
• Filed: 11/08/2001
• Issued: 08/24/2004
• Est. Priority Date: 05/29/2001
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Lewis, Monica
• Application Number:
  US09/986,277
• Publication Number:
  US 20020179976A1
• Time in Patent Office: 1,020 Days
• Field of Search: 257/330, 257/331, 257/370, 257/371, 257/565
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

It is an object to obtain a semiconductor device capable of minimizing an increase in a gate capacity without adversely influencing an operation characteristic and a method of manufacturing the semiconductor device. A first trench (7) and a second trench (11) are formed to reach an upper layer portion of an N⁻ layer (3) through a P base layer (5) and an N layer (4), respectively. In this case, a predetermined number of second trenches (11) are formed between the first trenches (7) and (7). The first trench (7) is provided adjacently to an N⁺ emitter region (6) and has a gate electrode (9) formed therein. The second trench (11) has a polysilicon region (15) formed therein. The second trench (11) is different from the first trench (7) in that the N⁺ emitter region (6) is not formed in a vicinal region and the gate electrode (9) is not formed therein. A trench space between the first trench (7) and the second trench (11) which are provided adjacently to each other is set to be such a distance as not to reduce a breakdown voltage. An emitter electrode (12) is directly formed on an almost whole surface of a base region (5).

Claims

1. A semiconductor device comprising:

a first semiconductor layer of a first conductivity type having first and second major surfaces;

a second semiconductor layer of a second conductivity type formed on the first major surface of said first semiconductor layer;

a third semiconductor layer of the second conductivity type formed on said second semiconductor layer;

a fourth semiconductor layer of the first conductivity type formed on said third semiconductor layer;

at least one first trench and at least one second trench arranged to penetrate through at least said fourth semiconductor layer from a surface of said fourth semiconductor layer such that a bottom part of an external wall of said at least one second trench is in direct contact with a region of the second conductivity type;

a first semiconductor region of the second conductivity type selectively formed in said surface of said fourth semiconductor layer vicinal to said at least one first trench;

a first insulating film formed on an internal wall of said at least one first trench;

a first material serving as a control electrode buried in said at least one first trench and formed on said first insulating film;

a second material formed in said at least one second trench, the second material not being a control electrode;

a first main electrode electrically connected to said second material formed in said at least one second trench and to at least a part of said first semiconductor region and formed over a surface of said fourth semiconductor layer; and

a second main electrode formed on the second major surface of said first semiconductor layer.

2. The semiconductor device according to claim 1, wherein a distance between said at least one first trench and said at least one second trench is 5 μ

m or less.

3. The semiconductor device according to claim 1, wherein

said at least one first trench includes a trench formed in a predetermined direction along a surface of said fourth semiconductor layer,

said at least one second trench includes a trench formed in said predetermined direction,

said first semiconductor region includes a first section formed in a vicinity of said at least one first trench and a second section extended from said first section in such a direction as to go away from said at least one first trench, and

said first main electrode is directly formed on said second section to carry out an electrical connection to said first semiconductor region.

4. The semiconductor device according to claim 3, wherein

said first semiconductor region includes a third section which is further extended from said second section and is formed in a vicinity of said at least one second trench, and

said first main electrode is further formed directly on said third section to carry out said electrical connection to said first semiconductor region.

5. The semiconductor device according to claim 4, wherein said second and third sections include a plurality of second and third sections respectively, and

said plurality of third sections are selectively formed in the vicinity of said at least one second trench.

6. The semiconductor device according to claim 1, further comprising:

a second semiconductor region of the first conductivity type formed in said surface of said fourth semiconductor layer contiguous to said at least one second trench, said second semiconductor region having a concentration of an impurity of the first conductivity type set to be higher than that of said fourth semiconductor layer.

7. The semiconductor device according to claim 6, wherein

said concentration of said impurity of the first conductivity type in said second semiconductor region is set to be higher than a concentration of an impurity of the second conductivity type in said first semiconductor region.

8. The semiconductor device according to claim 1, further comprising:

a plurality of second trenches.

9. The semiconductor device according to claim 1, wherein

said at least one first trench and said at least one second trench have equal formation widths.

10. The semiconductor device according to claim 1, further comprising:

a second insulating film formed on an internal wall of said at least one second trench.

11. The semiconductor device according to claim 10, further comprising a conductive region buried in said at least one second trench and formed on said second insulating film.

12. The semiconductor according to claim 11, wherein

said first main electrode is directly formed on said conductive region.

13. The semiconductor device according to claim 1, further comprising:

a sixth semiconductor layer of the second conductivity type formed between said first semiconductor layer and said second semiconductor layer, said sixth semiconductor layer having a concentration of an impurity of the second conductivity type higher than that of said second semiconductor layer.

14. The semiconductor device according to claim 1, wherein

said first semiconductor region is not vicinal to said at least one second trench.

15. The semiconductor device according to claim 14, wherein the first main electrode is formed in direct contact over an entire top surface of said fourth semiconductor layer around said at least one second trench.

16. The semiconductor device according to claim 15, wherein the first main electrode is formed in direct contact over entire said top surface of said fourth semiconductor layer between said at least one first trench and said at least one second trench.

17. The semiconductor device according to claim 1, further comprising:

a plurality of first trenches, wherein said at least one second trench is provided between two adjacent first trenches.

18. The semiconductor device according to claim 17, further comprising:

a plurality of second trenches provided between two adjacent first trenches.

19. The semiconductor device according to claim 18, wherein the first main electrode is formed in direct contact over an entire top surface of said fourth semiconductor layer among said plurality of second trenches.

20. The semiconductor device according to claim 19, wherein the first main electrode is formed in direct contact over entire said top surface of said fourth semiconductor layer between each first trench of said plurality of first trenches and each second trench of said plurality of second trenches.

21. The semiconductor device according to claim 17, wherein the first main electrode is formed in direct contact over an entire top surface of said fourth semiconductor layer around said at least one second trench.

22. The semiconductor device according to claim 21, wherein the first main electrode is formed in direct contact over entire said top surface of said fourth semiconductor layer between each first trench of said plurality of first trenches and said at least one second trench.

23. The semiconductor device according to claim 1, wherein the first main electrode is formed in direct contact over an entire top surface of said fourth semiconductor layer around said at least one second trench.

24. The semiconductor device according to claim 23, wherein the first main electrode is formed in direct contact over entire said top surface of said fourth semiconductor layer between said at least one first trench and said at least one second trench.

25. The semiconductor device according to claim 1, wherein

said first material is identical to said second material.