PWM controller having a modulator for saving power and reducing acoustic noise

• US 6,781,356 B1
• Filed: 03/24/2003
• Issued: 08/24/2004
• Est. Priority Date: 03/24/2003
• Status: Expired due to Fees

• Current Assignee: Fairchild Taiwan Corp (ON Semiconductor Corporation)
• Original Assignee: System General Corporation (ON Semiconductor Corporation)
• Inventors: Yang, Ta-yung, Chen, Chem-Lin, Lin, Jenn-yu G.
• Primary Examiner(s): Patel, Rajnikant B.
• Application Number:
  US10/249,217
• Time in Patent Office: 519 Days
• Field of Search: 323/282, 323/283, 323/284, 323/285, 323/286, 323/222, 323/290
• US Class Current: 323/282
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 1/0041 Control circuits in which a clock signal is selectively enabled or disabled
• CPC Class Codes: H02M 1/40 Means for preventing magnetic saturation
• CPC Class Codes: H02M 1/44 Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A modulator of a PWM controller is provided for saving power and reducing acoustic noise in the light load and no load conditions. The maximum on-time is kept as a constant and a bias current of the oscillator in the PWM controller is moderated to achieve the off-time modulation. The bias current is a function of the supply voltage and the feedback voltage, which is derived from a voltage feedback loop. A threshold voltage defines the level of the light load. A limit voltage defines the low level of the supply voltage. A bias current synthesizer generates the bias current. Reducing the bias current increases the off-time of the switching period. Once the feedback voltage is decreased lower than the threshold voltage, the bias current is reduced linearly and the off-time of the switching period is increased gradually. When the supply voltage is lower than the limit voltage, the bias current increases and determines a maximum off-time of the switching period. Keeping the maximum on-time as a constant and increasing the switching period by only increasing the off-time prevents magnetic components, such as inductors and transformers, from being saturated. Furthermore, a control circuit disables the oscillator as the PWM frequency may fall into the audio band, therefore the acoustic noise can be greatly reduced in the light load and no load conditions.

Claims

1. A pulse width modulation(PWM) controller having a modulator for saving power and reducing acoustic noise comprising:

a bias current synthesizer having four input terminals and two output terminals, wherein, a first output terminal of the bias current synthesizer generates a bias current that determines an off-time of a PWM switching period and a second output terminal of the bias current synthesizer outputs a reference current;

an oscillator having two input terminals, wherein a first input terminal of the oscillator is connected to the first output terminal of the bias current synthesizer for generating a pulse-signal for PWM switching, an on-time of the pulse-signal is a constant and an off-time of the pulse-signal is increased as the bias current decreases, a second input terminal of the oscillator is used to turn on/off the oscillator;

a control circuit having an input terminal and an output terminal, wherein the input terminal of the control circuit is connected to the reference current, which is derived from the second output terminal of the bias current synthesizer, the output terminal of the control circuit is connected to the second input terminal of the oscillator;

a RS flip-flop for generating an on-off signal, wherein the RS flip-flop is set by the pulse-signal and reset by a feedback control;

an AND-gate having two input terminals for outputting a PWM signal, wherein a first input terminal of the AND-gate is connected to the pulse-signal and a second input terminal of the AND-gate is connected to the on-off signal;

a feedback voltage connected to a first input of the bias current synthesizer, wherein the feedback voltage is derived from the voltage feedback loop of the power supply for controlling the on-time of the PWM signal and regulating the output of the power supply;

a threshold voltage connected to a second input of the bias current synthesizer to determine the level of a light load condition;

a limit voltage connected to a third input of the bias current synthesizer to determine the level of a low supply voltage;

wherein the limit voltage is changed in every PWM switching cycle which affects the bias current to produce a variable PWM switching frequency when the PWM switching frequency is decreased in the light load and no load condition; and

a supply voltage connected to a fourth input of the bias current synthesizer, in which the supply voltage is the power supply voltage of the PWM controller;

wherein the bias current is a function of the feedback voltage, the threshold voltage, the supply voltage, and the limit voltage, such that when the feedback voltage is lower than the threshold voltage, the bias current starts to reduce in response to the decrease of the feedback voltage, and if the supply voltage is lower than the limit voltage, the bias current starts to increase in response to the decrease of the supply voltage.

2. The PWM controller as claimed in claim 1, wherein the bias current synthesizer comprising:

a first adder, operative to subtract the threshold voltage from the feedback voltage;

an attenuator for attenuating the supply voltage;

a second adder, operative to subtract the output of the attenuator from the limit voltage;

a first limiter for scaling and clamping the output of the first adder to a first differential signal, wherein the amplitude of the first differential signal is in the range of zero to a first-maximum, wherein the first-maximum determines the slope of the change of the bias current in response to the variation of the feedback voltage;

a second limiter for scaling and clamping the output of the second adder to a second differential signal, in which the amplitude of the second differential signal is in the range of zero to a second-maximum, where the second-maximum determines the slope of the change of the bias current in response to the variation of the supply voltage;

a third adder, whereby the first differential signal is added with the second differential signal;

a V-to-I converter for converting the output of the third adder to a V-to-I current; and

a third limiter for clamping the V-to-I current to generate the reference current and the bias current, in which the amplitude of the bias current is in the range of zero to a current-maximum, wherein the current-maximum determines the minimum off-time of the PWM switching period.

3. The PWM controller as claimed in claim 1, wherein the bias current synthesizer comprising:

a first operation amplifier having a positive input terminal, a negative input terminal and an output terminal, in which the positive input is connected to the feedback voltage;

a first buffer amplifier having a positive input terminal, a negative input terminal and an output terminal, in which the negative input terminal is connected to the output and the positive input terminal is connected to the threshold voltage;

a first V-to-I transistor having a gate, a source and a drain, in which the gate is driven by the output terminal of the first operation amplifier, and the source is connected to the negative input terminal of the first operation amplifier developing a first source follow circuit;

a first resistor connected between the output of the first buffer amplifier and the source of the first V-to-I transistor;

wherein the threshold voltage is subtracted from the feedback voltage via the first resistor generating a first-current;

an attenuator;

a second operation amplifier having a positive input terminal, a negative input terminal and an output terminal, in which the positive input terminal is connected to the limit voltage;

a second buffer amplifier having a positive input terminal, a negative input terminal and an output terminal, in which the negative input terminal is connected to the output terminal and the positive input terminal is connected to the supply voltage through the attenuator;

a second V-to-I transistor having a gate, a source and a drain, in which the gate is driven by the output of the second operation amplifier, and the source is connected to the negative input of the second operation amplifier developing a second source follow circuit;

a second resistor connected between the output terminal of the second buffer amplifier and the source of the second V-to-I transistor;

wherein the supply voltage attenuated by the attenuator is subtracted by the limit voltage via the second resistor generating a second current;

a first-input transistor having a gate, a source and a drain;

a first-output transistor having a gate, a source and a drain, in which the source of the first-input transistor and the source of the first-output transistor are connected together, wherein the drain of the first V-to-I transistor, the drain of the first-input transistor, the gate of the first-input transistor and the gate of the first-output transistor are connected together to form a first mirror amplifier;

wherein the first current drives the first mirror amplifier to generate a mirroredFB-current;

a second-input transistor having a gate, a source and a drain;

a second-output transistor having a gate, a source and a drain, in which the source of the second-input transistor and the source of the second-output transistor are connected together;

wherein the drain of the second V-to-I transistor, the drain of the second-input transistor, the gate of the second-input transistor and the gate of the second-output transistor are connected together to form a second mirror amplifier, wherein the second current drives the second mirror amplifier to generate a mirroredVCC-current;

a third output transistor having a gate, a source and a drain, in which the gate of the third output transistor is connected to the gate of the first input transistor, the source of the third output transistor is connected to the source of the first input transistor;

a fourth output transistor having a gate, a source and a drain, in which the gate of the fourth output transistor is connected to the gate of the second input transistor, the source of the fourth output transistor is connected to the source of the second input transistor, the drain of the fourth transistor and the drain of the third transistor are connected together to generate the reference current; and

a limit current-source connected to the source of the first-input transistor, the source of the first-output transistor, the source of the second-input transistor, the source of the second-output transistor, the source of the third output transistor and the source of the fourth output transistor for clamping the maximum output current of the bias current;

wherein the drain of the first-output transistor and the drain of the second-output transistor are connected together to sum the mirroredFB-current and the mirroredVCC-current and generate the bias current.

4. The PWM controller as claimed in claim 1, wherein the control circuit comprising:

a first switch having an input terminal, an output terminal and a control terminal;

a second switch having an input terminal, an output terminal and a control terminal;

a reference resistor for converting the reference current into a reference voltage;

a NOT gate having an output terminal connected to the control terminal of the first switch and an input terminal;

a comparator having a negative input terminal, a positive input terminal, and an output terminal, in which the negative input terminal is connected to the reference resistor;

the positive input terminal is connected to the output terminals of the first switch and the second switch;

the output terminal, which is connected to the input terminal of the NOT gate and the control terminal of the second switch, is applied to enable and disable the oscillation of the oscillator.